fix some comments

Author: LiqinWeng

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -17930,7 +17930,6 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
 
   SDValue ShiftLHS = N->getOperand(0);
   EVT VT = N->getValueType(0);
-  SDValue Add;
 
   if (!ShiftLHS->hasOneUse())
     return false;
@@ -17957,7 +17956,6 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
       }
     }
   }
-
   return true;
 }
 

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

@@ -2154,19 +2154,20 @@ bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
 
 bool HexagonTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
-  using namespace llvm::SDPatternMatch;
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
-  SDValue Add;
 
-  if (ShiftLHS->hasOneUse() ||
-      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
-    return true;
+  if (!ShiftLHS->hasOneUse())
+    return false;
 
-  return false;
+  if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
+       !ShiftLHS.getOperand(0)->hasOneUse()))
+    return false;
+
+  return true;
 }
 
 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -19169,17 +19169,17 @@ Value *PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
 
 bool PPCTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
-  using namespace llvm::SDPatternMatch;
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
-  SDValue Add;
+  if (!ShiftLHS->hasOneUse())
+    return false;
 
-  if (ShiftLHS->hasOneUse() ||
-      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
-    return true;
+  if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
+       !ShiftLHS.getOperand(0)->hasOneUse()))
+    return false;
 
-  return false;
+  return true;
 }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -18226,13 +18226,12 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     }
   }
 
-  if ((N0->getOpcode() == ISD::ADD || N0->getOpcode() == ISD::OR) &&
-      !N0->hasOneUse())
+  if (!N0->hasOneUse())
     return false;
 
   if (N0->getOpcode() == ISD::SIGN_EXTEND &&
       N0->getOperand(0)->getOpcode() == ISD::ADD &&
-      !(N0->hasOneUse() && N0->getOperand(0)->hasOneUse()))
+      !N0->getOperand(0)->hasOneUse())
     return isLDST();
 
   return true;

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -60676,17 +60676,17 @@ Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
 
 bool X86TargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
-  using namespace llvm::SDPatternMatch;
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
-  SDValue Add;
+  if (!ShiftLHS->hasOneUse())
+    return false;
 
-  if (ShiftLHS->hasOneUse() ||
-      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
-    return true;
+  if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
+       !ShiftLHS.getOperand(0)->hasOneUse()))
+    return false;
 
-  return false;
+  return true;
 }

llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV64 %s
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
 
 define void @add_sext_shl_moreOneUse_add(ptr %array1, i32 %a, i32 %b) {
 ; RV64-LABEL: add_sext_shl_moreOneUse_add:

llvm/test/CodeGen/RISCV/add_shl_constant.ll

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32 %s
+; RUN: llc -mtriple=riscv32  < %s | FileCheck -check-prefix=RV32 %s
 
 define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind {
 ; RV32-LABEL: add_shl_oneUse: