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[Clang][PowerPC] Add __dmr2048 type and DMF crypto builtins (#157152)
Define the __dmr2048 type to represent the DMR pair introduced by the Dense Math Facility on PowerPC, and add three Clang builtins corresponding to DMF cryptography: __builtin_mma_dmsha2hash __builtin_mma_dmsha3hash __builtin_mma_dmxxshapad The __dmr2048 type is required for the dmsha3hash crypto builtin, and, as withother PPC MMA and DMR types, its use is strongly restricted.
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12 files changed

+356
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‎clang/include/clang/Basic/BuiltinsPPC.def‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,6 +1105,13 @@ UNALIASED_CUSTOM_BUILTIN(mma_disassemble_dmr, "vv*W1024*", false,
11051105
UNALIASED_CUSTOM_BUILTIN(mma_build_dmr, "vW1024*VVVVVVVV", false,
11061106
"mma,isa-future-instructions")
11071107

1108+
UNALIASED_CUSTOM_BUILTIN(mma_dmsha2hash, "vW1024*W1024*Ii", true,
1109+
"mma,isa-future-instructions")
1110+
UNALIASED_CUSTOM_BUILTIN(mma_dmsha3hash, "vW2048*Ii", true,
1111+
"mma,isa-future-instructions")
1112+
UNALIASED_CUSTOM_BUILTIN(mma_dmxxshapad, "vW1024*VIiIiIi", true,
1113+
"mma,isa-future-instructions")
1114+
11081115
// MMA builtins with positive/negative multiply/accumulate.
11091116
UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf16ger2, "vW512*VV",
11101117
"mma,paired-vector-memops")

‎clang/include/clang/Basic/PPCTypes.def‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
#endif
3131

3232

33+
PPC_VECTOR_MMA_TYPE(__dmr2048, DMR2048, 2048)
3334
PPC_VECTOR_MMA_TYPE(__dmr1024, DMR1024, 1024)
3435
PPC_VECTOR_MMA_TYPE(__vector_quad, VectorQuad, 512)
3536
PPC_VECTOR_VSX_TYPE(__vector_pair, VectorPair, 256)

‎clang/include/clang/Serialization/ASTBitCodes.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1160,7 +1160,7 @@ enum PredefinedTypeIDs {
11601160
///
11611161
/// Type IDs for non-predefined types will start at
11621162
/// NUM_PREDEF_TYPE_IDs.
1163-
const unsigned NUM_PREDEF_TYPE_IDS = 513;
1163+
const unsigned NUM_PREDEF_TYPE_IDS = 514;
11641164

11651165
// Ensure we do not overrun the predefined types we reserved
11661166
// in the enum PredefinedTypeIDs above.

‎clang/lib/AST/ASTContext.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3501,6 +3501,7 @@ static void encodeTypeForFunctionPointerAuth(const ASTContext &Ctx,
35013501
case BuiltinType::VectorQuad:
35023502
case BuiltinType::VectorPair:
35033503
case BuiltinType::DMR1024:
3504+
case BuiltinType::DMR2048:
35043505
OS << "?";
35053506
return;
35063507

‎clang/lib/CodeGen/TargetBuiltins/PPC.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1153,7 +1153,8 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
11531153
}
11541154
if (BuiltinID == PPC::BI__builtin_mma_dmmr ||
11551155
BuiltinID == PPC::BI__builtin_mma_dmxor ||
1156-
BuiltinID == PPC::BI__builtin_mma_disassemble_dmr) {
1156+
BuiltinID == PPC::BI__builtin_mma_disassemble_dmr ||
1157+
BuiltinID == PPC::BI__builtin_mma_dmsha2hash) {
11571158
Address Addr = EmitPointerWithAlignment(E->getArg(1));
11581159
Ops[1] = Builder.CreateLoad(Addr);
11591160
}

‎clang/test/AST/ast-dump-ppc-types.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
// are correctly defined. We also added checks on a couple of other targets to
1818
// ensure the types are target-dependent.
1919

20+
// CHECK: TypedefDecl {{.*}} implicit __dmr2048 '__dmr2048'
21+
// CHECK: `-BuiltinType {{.*}} '__dmr2048'
2022
// CHECK: TypedefDecl {{.*}} implicit __dmr1024 '__dmr1024'
2123
// CHECK: `-BuiltinType {{.*}} '__dmr1024'
2224
// CHECK: TypedefDecl {{.*}} implicit __vector_quad '__vector_quad'

‎clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -208,6 +208,75 @@ void test_dmf_basic2(char *p1, char *res1, char *res2,
208208
__builtin_mma_build_dmr((__dmr1024*)res2, vv, vv, vv, vv, vv, vv, vv, vv);
209209
__builtin_mma_disassemble_dmr(res1, (__dmr1024*)p1);
210210
}
211+
212+
// CHECK-LABEL: define dso_local void @test_dmsha2hash(
213+
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
214+
// CHECK-NEXT: [[ENTRY:.*:]]
215+
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA6]]
216+
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA6]]
217+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
218+
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA6]]
219+
// CHECK-NEXT: ret void
220+
//
221+
// AIX-LABEL: define void @test_dmsha2hash(
222+
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
223+
// AIX-NEXT: [[ENTRY:.*:]]
224+
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA6]]
225+
// AIX-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA6]]
226+
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
227+
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA6]]
228+
// AIX-NEXT: ret void
229+
//
230+
void test_dmsha2hash(unsigned char *vdmrp1, unsigned char *vdmrp2, unsigned char *resp) {
231+
__dmr1024 vdmr1 = *((__dmr1024 *)vdmrp1);
232+
__dmr1024 vdmr2 = *((__dmr1024 *)vdmrp2);
233+
__builtin_mma_dmsha2hash(&vdmr1, &vdmr2, 1);
234+
*((__dmr1024 *)resp) = vdmr1;
235+
}
236+
237+
// CHECK-LABEL: define dso_local void @test_dmsha3hash(
238+
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
239+
// CHECK-NEXT: [[ENTRY:.*:]]
240+
// CHECK-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA9:![0-9]+]]
241+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 4)
242+
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA9]]
243+
// CHECK-NEXT: ret void
244+
//
245+
// AIX-LABEL: define void @test_dmsha3hash(
246+
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
247+
// AIX-NEXT: [[ENTRY:.*:]]
248+
// AIX-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA9:![0-9]+]]
249+
// AIX-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 4)
250+
// AIX-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA9]]
251+
// AIX-NEXT: ret void
252+
//
253+
void test_dmsha3hash(unsigned char *vdmrpp, unsigned char *resp) {
254+
__dmr2048 vdmrp = *((__dmr2048 *)vdmrpp);
255+
__builtin_mma_dmsha3hash(&vdmrp, 4);
256+
*((__dmr2048 *)resp) = vdmrp;
257+
}
258+
259+
// CHECK-LABEL: define dso_local void @test_dmxxshapad(
260+
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
261+
// CHECK-NEXT: [[ENTRY:.*:]]
262+
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA6]]
263+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 1, i32 5)
264+
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA6]]
265+
// CHECK-NEXT: ret void
266+
//
267+
// AIX-LABEL: define void @test_dmxxshapad(
268+
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
269+
// AIX-NEXT: [[ENTRY:.*:]]
270+
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA6]]
271+
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 1, i32 5)
272+
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA6]]
273+
// AIX-NEXT: ret void
274+
//
275+
void test_dmxxshapad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
276+
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
277+
__builtin_mma_dmxxshapad(&vdmr, vc, 2, 1, 5);
278+
*((__dmr1024 *)resp) = vdmr;
279+
}
211280
//.
212281
// CHECK: [[__VECTOR_PAIR_TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
213282
// CHECK: [[META3]] = !{!"__vector_pair", [[META4:![0-9]+]], i64 0}
@@ -216,6 +285,8 @@ void test_dmf_basic2(char *p1, char *res1, char *res2,
216285
// CHECK: [[__DMR1024_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
217286
// CHECK: [[META7]] = !{!"__dmr1024", [[META4]], i64 0}
218287
// CHECK: [[CHAR_TBAA8]] = !{[[META4]], [[META4]], i64 0}
288+
// CHECK: [[__DMR2048_TBAA9]] = !{[[META10:![0-9]+]], [[META10]], i64 0}
289+
// CHECK: [[META10]] = !{!"__dmr2048", [[META4]], i64 0}
219290
//.
220291
// AIX: [[__VECTOR_PAIR_TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
221292
// AIX: [[META3]] = !{!"__vector_pair", [[META4:![0-9]+]], i64 0}
@@ -224,4 +295,6 @@ void test_dmf_basic2(char *p1, char *res1, char *res2,
224295
// AIX: [[__DMR1024_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
225296
// AIX: [[META7]] = !{!"__dmr1024", [[META4]], i64 0}
226297
// AIX: [[CHAR_TBAA8]] = !{[[META4]], [[META4]], i64 0}
298+
// AIX: [[__DMR2048_TBAA9]] = !{[[META10:![0-9]+]], [[META10]], i64 0}
299+
// AIX: [[META10]] = !{!"__dmr2048", [[META4]], i64 0}
227300
//.

‎clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,9 @@
99
// RUN: FileCheck --check-prefix=ISA_FUTURE %s
1010

1111
//__attribute__((target("no-mma")))
12-
void test_mma(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc) {
12+
__attribute__((target("no-mma")))
13+
void test_mma(unsigned char *vdmrpp, unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc) {
14+
__dmr2048 vdmrpair = *((__dmr2048 *)vdmrpp);
1315
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
1416
__vector_pair vp = *((__vector_pair *)vpp);
1517
__builtin_mma_dmxvi8gerx4(&vdmr, vp, vc);
@@ -23,6 +25,9 @@ void test_mma(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc)
2325
__builtin_mma_dmxor(&vdmr, (__dmr1024*)vpp);
2426
__builtin_mma_build_dmr(&vdmr, vc, vc, vc, vc, vc, vc, vc, vc);
2527
__builtin_mma_disassemble_dmr(vdmrp, &vdmr);
28+
__builtin_mma_dmsha2hash(&vdmr, &vdmr, 0);
29+
__builtin_mma_dmsha3hash(&vdmrpair, 0);
30+
__builtin_mma_dmxxshapad(&vdmr, vc, 0, 0, 0);
2631

2732
// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature mma,paired-vector-memops
2833
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature mma,paired-vector-memops
@@ -35,6 +40,9 @@ void test_mma(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc)
3540
// ISA_FUTURE: error: '__builtin_mma_dmxor' needs target feature mma,isa-future-instructions
3641
// ISA_FUTURE: error: '__builtin_mma_build_dmr' needs target feature mma,isa-future-instructions
3742
// ISA_FUTURE: error: '__builtin_mma_disassemble_dmr' needs target feature mma,isa-future-instructions
43+
// CHECK: error: '__builtin_mma_dmsha2hash' needs target feature mma,isa-future-instructions
44+
// CHECK: error: '__builtin_mma_dmsha3hash' needs target feature mma,isa-future-instructions
45+
// CHECK: error: '__builtin_mma_dmxxshapad' needs target feature mma,isa-future-instructions
3846

3947
// DMF VSX Vector bfloat16 GER 2x builtins.
4048

‎clang/test/CodeGen/PowerPC/ppc-dmf-types.c‎

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,162 @@
22
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
33
// RUN: -emit-llvm -o - %s | FileCheck %s
44

5+
// CHECK-LABEL: @test_dmrp_copy(
6+
// CHECK-NEXT: entry:
7+
// CHECK-NEXT: [[PTR1_ADDR:%.*]] = alloca ptr, align 8
8+
// CHECK-NEXT: [[PTR2_ADDR:%.*]] = alloca ptr, align 8
9+
// CHECK-NEXT: store ptr [[PTR1:%.*]], ptr [[PTR1_ADDR]], align 8
10+
// CHECK-NEXT: store ptr [[PTR2:%.*]], ptr [[PTR2_ADDR]], align 8
11+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 8
12+
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <2048 x i1>, ptr [[TMP0]], i64 2
13+
// CHECK-NEXT: [[TMP1:%.*]] = load <2048 x i1>, ptr [[ADD_PTR]], align 256
14+
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8
15+
// CHECK-NEXT: [[ADD_PTR1:%.*]] = getelementptr inbounds <2048 x i1>, ptr [[TMP2]], i64 1
16+
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[ADD_PTR1]], align 256
17+
// CHECK-NEXT: ret void
18+
//
19+
void test_dmrp_copy(__dmr2048 *ptr1, __dmr2048 *ptr2) {
20+
*(ptr2 + 1) = *(ptr1 + 2);
21+
}
22+
23+
// CHECK-LABEL: @test_dmrp_typedef(
24+
// CHECK-NEXT: entry:
25+
// CHECK-NEXT: [[INP_ADDR:%.*]] = alloca ptr, align 8
26+
// CHECK-NEXT: [[OUTP_ADDR:%.*]] = alloca ptr, align 8
27+
// CHECK-NEXT: [[VDMRPIN:%.*]] = alloca ptr, align 8
28+
// CHECK-NEXT: [[VDMRPOUT:%.*]] = alloca ptr, align 8
29+
// CHECK-NEXT: store ptr [[INP:%.*]], ptr [[INP_ADDR]], align 8
30+
// CHECK-NEXT: store ptr [[OUTP:%.*]], ptr [[OUTP_ADDR]], align 8
31+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[INP_ADDR]], align 8
32+
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPIN]], align 8
33+
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUTP_ADDR]], align 8
34+
// CHECK-NEXT: store ptr [[TMP1]], ptr [[VDMRPOUT]], align 8
35+
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VDMRPIN]], align 8
36+
// CHECK-NEXT: [[TMP3:%.*]] = load <2048 x i1>, ptr [[TMP2]], align 256
37+
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VDMRPOUT]], align 8
38+
// CHECK-NEXT: store <2048 x i1> [[TMP3]], ptr [[TMP4]], align 256
39+
// CHECK-NEXT: ret void
40+
//
41+
void test_dmrp_typedef(int *inp, int *outp) {
42+
__dmr2048 *vdmrpin = (__dmr2048 *)inp;
43+
__dmr2048 *vdmrpout = (__dmr2048 *)outp;
44+
*vdmrpout = *vdmrpin;
45+
}
46+
47+
// CHECK-LABEL: @test_dmrp_arg(
48+
// CHECK-NEXT: entry:
49+
// CHECK-NEXT: [[VDMRP_ADDR:%.*]] = alloca ptr, align 8
50+
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
51+
// CHECK-NEXT: [[VDMRPP:%.*]] = alloca ptr, align 8
52+
// CHECK-NEXT: store ptr [[VDMRP:%.*]], ptr [[VDMRP_ADDR]], align 8
53+
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
54+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
55+
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPP]], align 8
56+
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP_ADDR]], align 8
57+
// CHECK-NEXT: [[TMP2:%.*]] = load <2048 x i1>, ptr [[TMP1]], align 256
58+
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRPP]], align 8
59+
// CHECK-NEXT: store <2048 x i1> [[TMP2]], ptr [[TMP3]], align 256
60+
// CHECK-NEXT: ret void
61+
//
62+
void test_dmrp_arg(__dmr2048 *vdmrp, int *ptr) {
63+
__dmr2048 *vdmrpp = (__dmr2048 *)ptr;
64+
*vdmrpp = *vdmrp;
65+
}
66+
67+
// CHECK-LABEL: @test_dmrp_const_arg(
68+
// CHECK-NEXT: entry:
69+
// CHECK-NEXT: [[VDMRP_ADDR:%.*]] = alloca ptr, align 8
70+
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
71+
// CHECK-NEXT: [[VDMRPP:%.*]] = alloca ptr, align 8
72+
// CHECK-NEXT: store ptr [[VDMRP:%.*]], ptr [[VDMRP_ADDR]], align 8
73+
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
74+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
75+
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPP]], align 8
76+
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP_ADDR]], align 8
77+
// CHECK-NEXT: [[TMP2:%.*]] = load <2048 x i1>, ptr [[TMP1]], align 256
78+
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRPP]], align 8
79+
// CHECK-NEXT: store <2048 x i1> [[TMP2]], ptr [[TMP3]], align 256
80+
// CHECK-NEXT: ret void
81+
//
82+
void test_dmrp_const_arg(const __dmr2048 *const vdmrp, int *ptr) {
83+
__dmr2048 *vdmrpp = (__dmr2048 *)ptr;
84+
*vdmrpp = *vdmrp;
85+
}
86+
87+
// CHECK-LABEL: @test_dmrp_array_arg(
88+
// CHECK-NEXT: entry:
89+
// CHECK-NEXT: [[VDMRPA_ADDR:%.*]] = alloca ptr, align 8
90+
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
91+
// CHECK-NEXT: [[VDMRPP:%.*]] = alloca ptr, align 8
92+
// CHECK-NEXT: store ptr [[VDMRPA:%.*]], ptr [[VDMRPA_ADDR]], align 8
93+
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
94+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
95+
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPP]], align 8
96+
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRPA_ADDR]], align 8
97+
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <2048 x i1>, ptr [[TMP1]], i64 0
98+
// CHECK-NEXT: [[TMP2:%.*]] = load <2048 x i1>, ptr [[ARRAYIDX]], align 256
99+
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRPP]], align 8
100+
// CHECK-NEXT: store <2048 x i1> [[TMP2]], ptr [[TMP3]], align 256
101+
// CHECK-NEXT: ret void
102+
//
103+
void test_dmrp_array_arg(__dmr2048 vdmrpa[], int *ptr) {
104+
__dmr2048 *vdmrpp = (__dmr2048 *)ptr;
105+
*vdmrpp = vdmrpa[0];
106+
}
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108+
// CHECK-LABEL: @test_dmrp_ret_const(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[VDMRPP:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPP]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRPP]], align 8
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// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <2048 x i1>, ptr [[TMP1]], i64 2
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// CHECK-NEXT: ret ptr [[ADD_PTR]]
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//
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const __dmr2048 *test_dmrp_ret_const(int *ptr) {
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__dmr2048 *vdmrpp = (__dmr2048 *)ptr;
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return vdmrpp + 2;
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}
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// CHECK-LABEL: @test_dmrp_sizeof_alignof(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[VDMRPP:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[VDMRP:%.*]] = alloca <2048 x i1>, align 256
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// CHECK-NEXT: [[SIZET:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[ALIGNT:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[SIZEV:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[ALIGNV:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRPP]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRPP]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <2048 x i1>, ptr [[TMP1]], align 256
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// CHECK-NEXT: store <2048 x i1> [[TMP2]], ptr [[VDMRP]], align 256
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// CHECK-NEXT: store i32 256, ptr [[SIZET]], align 4
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// CHECK-NEXT: store i32 256, ptr [[ALIGNT]], align 4
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// CHECK-NEXT: store i32 256, ptr [[SIZEV]], align 4
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// CHECK-NEXT: store i32 256, ptr [[ALIGNV]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIZET]], align 4
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNT]], align 4
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// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP3]], [[TMP4]]
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// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIZEV]], align 4
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// CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ADD]], [[TMP5]]
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// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ALIGNV]], align 4
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// CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[TMP6]]
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// CHECK-NEXT: ret i32 [[ADD2]]
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//
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int test_dmrp_sizeof_alignof(int *ptr) {
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__dmr2048 *vdmrpp = (__dmr2048 *)ptr;
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__dmr2048 vdmrp = *vdmrpp;
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unsigned sizet = sizeof(__dmr2048);
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unsigned alignt = __alignof__(__dmr2048);
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unsigned sizev = sizeof(vdmrp);
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unsigned alignv = __alignof__(vdmrp);
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return sizet + alignt + sizev + alignv;
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}
5161

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// CHECK-LABEL: @test_dmr_copy(
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// CHECK-NEXT: entry:

‎clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,9 @@
77
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
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// RUN: -emit-llvm -o - | FileCheck %s
99

10+
// CHECK: _Z1fPu9__dmr2048
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void f(__dmr2048 *vdmrp) {}
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1013
// CHECK: _Z2f0Pu9__dmr1024
1114
void f0(__dmr1024 *vdmr) {}
1215

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