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[RISCV][GISel] Enable shift_immed_chain in RISCVPostLegalizerCombiner
This helps combine back to back shifts that may get created when sext_inreg is legalized.
1 parent cb98366 commit ff98efa

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6 files changed

+25
-41
lines changed

6 files changed

+25
-41
lines changed

‎llvm/lib/Target/RISCV/RISCVCombine.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,6 @@ def RISCVO0PreLegalizerCombiner: GICombiner<
2424
def RISCVPostLegalizerCombiner
2525
: GICombiner<"RISCVPostLegalizerCombinerImpl",
2626
[sub_to_add, combines_for_extload, redundant_and,
27-
identity_combines, commute_constant_to_rhs,
27+
identity_combines, shift_immed_chain, commute_constant_to_rhs,
2828
constant_fold_cast_op]> {
2929
}

‎llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,7 @@ define i8 @abs8(i8 %x) {
1717
; RV32I-LABEL: abs8:
1818
; RV32I: # %bb.0:
1919
; RV32I-NEXT: slli a1, a0, 24
20-
; RV32I-NEXT: srai a1, a1, 24
21-
; RV32I-NEXT: srai a1, a1, 7
20+
; RV32I-NEXT: srai a1, a1, 31
2221
; RV32I-NEXT: add a0, a0, a1
2322
; RV32I-NEXT: xor a0, a0, a1
2423
; RV32I-NEXT: ret
@@ -33,8 +32,7 @@ define i8 @abs8(i8 %x) {
3332
; RV64I-LABEL: abs8:
3433
; RV64I: # %bb.0:
3534
; RV64I-NEXT: slli a1, a0, 24
36-
; RV64I-NEXT: sraiw a1, a1, 24
37-
; RV64I-NEXT: sraiw a1, a1, 7
35+
; RV64I-NEXT: sraiw a1, a1, 31
3836
; RV64I-NEXT: addw a0, a0, a1
3937
; RV64I-NEXT: xor a0, a0, a1
4038
; RV64I-NEXT: ret
@@ -53,8 +51,7 @@ define i16 @abs16(i16 %x) {
5351
; RV32I-LABEL: abs16:
5452
; RV32I: # %bb.0:
5553
; RV32I-NEXT: slli a1, a0, 16
56-
; RV32I-NEXT: srai a1, a1, 16
57-
; RV32I-NEXT: srai a1, a1, 15
54+
; RV32I-NEXT: srai a1, a1, 31
5855
; RV32I-NEXT: add a0, a0, a1
5956
; RV32I-NEXT: xor a0, a0, a1
6057
; RV32I-NEXT: ret
@@ -69,8 +66,7 @@ define i16 @abs16(i16 %x) {
6966
; RV64I-LABEL: abs16:
7067
; RV64I: # %bb.0:
7168
; RV64I-NEXT: slli a1, a0, 16
72-
; RV64I-NEXT: sraiw a1, a1, 16
73-
; RV64I-NEXT: sraiw a1, a1, 15
69+
; RV64I-NEXT: sraiw a1, a1, 31
7470
; RV64I-NEXT: addw a0, a0, a1
7571
; RV64I-NEXT: xor a0, a0, a1
7672
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll‎

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -335,13 +335,11 @@ define i8 @srli_i8(i8 %a) nounwind {
335335
}
336336

337337
; FIXME: We should use slli+srai with Zbb for better compression.
338-
; FIXME: We should combine back to back srai.
339338
define i8 @srai_i8(i8 %a) nounwind {
340339
; RV32I-LABEL: srai_i8:
341340
; RV32I: # %bb.0:
342341
; RV32I-NEXT: slli a0, a0, 24
343-
; RV32I-NEXT: srai a0, a0, 24
344-
; RV32I-NEXT: srai a0, a0, 5
342+
; RV32I-NEXT: srai a0, a0, 29
345343
; RV32I-NEXT: ret
346344
;
347345
; RV32ZBB-LABEL: srai_i8:
@@ -353,8 +351,7 @@ define i8 @srai_i8(i8 %a) nounwind {
353351
; RV32ZBKB-LABEL: srai_i8:
354352
; RV32ZBKB: # %bb.0:
355353
; RV32ZBKB-NEXT: slli a0, a0, 24
356-
; RV32ZBKB-NEXT: srai a0, a0, 24
357-
; RV32ZBKB-NEXT: srai a0, a0, 5
354+
; RV32ZBKB-NEXT: srai a0, a0, 29
358355
; RV32ZBKB-NEXT: ret
359356
%1 = ashr i8 %a, 5
360357
ret i8 %1
@@ -380,13 +377,11 @@ define i16 @srli_i16(i16 %a) nounwind {
380377
}
381378

382379
; FIXME: We should use slli+srai with Zbb/Zbkb for better compression.
383-
; FIXME: We should combine back to back sraiw.
384380
define i16 @srai_i16(i16 %a) nounwind {
385381
; RV32I-LABEL: srai_i16:
386382
; RV32I: # %bb.0:
387383
; RV32I-NEXT: slli a0, a0, 16
388-
; RV32I-NEXT: srai a0, a0, 16
389-
; RV32I-NEXT: srai a0, a0, 9
384+
; RV32I-NEXT: srai a0, a0, 25
390385
; RV32I-NEXT: ret
391386
;
392387
; RV32ZBB-LABEL: srai_i16:
@@ -398,8 +393,7 @@ define i16 @srai_i16(i16 %a) nounwind {
398393
; RV32ZBKB-LABEL: srai_i16:
399394
; RV32ZBKB: # %bb.0:
400395
; RV32ZBKB-NEXT: slli a0, a0, 16
401-
; RV32ZBKB-NEXT: srai a0, a0, 16
402-
; RV32ZBKB-NEXT: srai a0, a0, 9
396+
; RV32ZBKB-NEXT: srai a0, a0, 25
403397
; RV32ZBKB-NEXT: ret
404398
%1 = ashr i16 %a, 9
405399
ret i16 %1

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -620,9 +620,9 @@ define i32 @sextb_i32(i32 %a) nounwind {
620620
define i64 @sextb_i64(i64 %a) nounwind {
621621
; RV32I-LABEL: sextb_i64:
622622
; RV32I: # %bb.0:
623-
; RV32I-NEXT: slli a0, a0, 24
624-
; RV32I-NEXT: srai a0, a0, 24
625-
; RV32I-NEXT: srai a1, a0, 31
623+
; RV32I-NEXT: slli a1, a0, 24
624+
; RV32I-NEXT: srai a0, a1, 24
625+
; RV32I-NEXT: srai a1, a1, 31
626626
; RV32I-NEXT: ret
627627
;
628628
; RV32ZBB-LABEL: sextb_i64:
@@ -655,9 +655,9 @@ define i32 @sexth_i32(i32 %a) nounwind {
655655
define i64 @sexth_i64(i64 %a) nounwind {
656656
; RV32I-LABEL: sexth_i64:
657657
; RV32I: # %bb.0:
658-
; RV32I-NEXT: slli a0, a0, 16
659-
; RV32I-NEXT: srai a0, a0, 16
660-
; RV32I-NEXT: srai a1, a0, 31
658+
; RV32I-NEXT: slli a1, a0, 16
659+
; RV32I-NEXT: srai a0, a1, 16
660+
; RV32I-NEXT: srai a1, a1, 31
661661
; RV32I-NEXT: ret
662662
;
663663
; RV32ZBB-LABEL: sexth_i64:

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll‎

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -439,13 +439,11 @@ define i8 @srli_i8(i8 %a) nounwind {
439439
}
440440

441441
; FIXME: We should use slli+srai with Zbb for better compression.
442-
; FIXME: We should combine back to back sraiw.
443442
define i8 @srai_i8(i8 %a) nounwind {
444443
; RV64I-LABEL: srai_i8:
445444
; RV64I: # %bb.0:
446445
; RV64I-NEXT: slli a0, a0, 24
447-
; RV64I-NEXT: sraiw a0, a0, 24
448-
; RV64I-NEXT: sraiw a0, a0, 5
446+
; RV64I-NEXT: sraiw a0, a0, 29
449447
; RV64I-NEXT: ret
450448
;
451449
; RV64ZBB-LABEL: srai_i8:
@@ -457,8 +455,7 @@ define i8 @srai_i8(i8 %a) nounwind {
457455
; RV64ZBKB-LABEL: srai_i8:
458456
; RV64ZBKB: # %bb.0:
459457
; RV64ZBKB-NEXT: slli a0, a0, 24
460-
; RV64ZBKB-NEXT: sraiw a0, a0, 24
461-
; RV64ZBKB-NEXT: sraiw a0, a0, 5
458+
; RV64ZBKB-NEXT: sraiw a0, a0, 29
462459
; RV64ZBKB-NEXT: ret
463460
%1 = ashr i8 %a, 5
464461
ret i8 %1
@@ -492,13 +489,11 @@ define i16 @srli_i16(i16 %a) nounwind {
492489
}
493490

494491
; FIXME: We should use slli+srai with Zbb/Zbkb for better compression.
495-
; FIXME: We should combine back to back sraiw.
496492
define i16 @srai_i16(i16 %a) nounwind {
497493
; RV64I-LABEL: srai_i16:
498494
; RV64I: # %bb.0:
499495
; RV64I-NEXT: slli a0, a0, 16
500-
; RV64I-NEXT: sraiw a0, a0, 16
501-
; RV64I-NEXT: sraiw a0, a0, 9
496+
; RV64I-NEXT: sraiw a0, a0, 25
502497
; RV64I-NEXT: ret
503498
;
504499
; RV64ZBB-LABEL: srai_i16:
@@ -510,8 +505,7 @@ define i16 @srai_i16(i16 %a) nounwind {
510505
; RV64ZBKB-LABEL: srai_i16:
511506
; RV64ZBKB: # %bb.0:
512507
; RV64ZBKB-NEXT: slli a0, a0, 16
513-
; RV64ZBKB-NEXT: sraiw a0, a0, 16
514-
; RV64ZBKB-NEXT: sraiw a0, a0, 9
508+
; RV64ZBKB-NEXT: sraiw a0, a0, 25
515509
; RV64ZBKB-NEXT: ret
516510
%1 = ashr i16 %a, 9
517511
ret i16 %1

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -270,17 +270,17 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
270270
define i32 @ctlz_lshr_i32(i32 signext %a) {
271271
; RV64I-LABEL: ctlz_lshr_i32:
272272
; RV64I: # %bb.0:
273-
; RV64I-NEXT: srliw a0, a0, 1
274-
; RV64I-NEXT: slli a1, a0, 32
275-
; RV64I-NEXT: srli a1, a1, 32
276-
; RV64I-NEXT: beqz a1, .LBB4_2
273+
; RV64I-NEXT: srliw a1, a0, 1
274+
; RV64I-NEXT: slli a2, a1, 32
275+
; RV64I-NEXT: srli a2, a2, 32
276+
; RV64I-NEXT: beqz a2, .LBB4_2
277277
; RV64I-NEXT: # %bb.1: # %cond.false
278278
; RV64I-NEXT: addi sp, sp, -16
279279
; RV64I-NEXT: .cfi_def_cfa_offset 16
280280
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
281281
; RV64I-NEXT: .cfi_offset ra, -8
282-
; RV64I-NEXT: srliw a1, a0, 1
283-
; RV64I-NEXT: or a0, a0, a1
282+
; RV64I-NEXT: srliw a0, a0, 2
283+
; RV64I-NEXT: or a0, a1, a0
284284
; RV64I-NEXT: srliw a1, a0, 2
285285
; RV64I-NEXT: or a0, a0, a1
286286
; RV64I-NEXT: srliw a1, a0, 4

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