Skip to content

Commit ffbba48

Browse files
committed
Address first round of review comments
1 parent 6dbd9ba commit ffbba48

File tree

4 files changed

+10
-10
lines changed

4 files changed

+10
-10
lines changed

clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@
204204
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
205205
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
206206
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
207-
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Small Integer New)
207+
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
208208
// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
209209
// CHECK-EMPTY:
210210
// CHECK-NEXT: Supported Profiles

llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1377,11 +1377,11 @@ def HasVendorXqcilo
13771377
// Rivos Extension(s)
13781378

13791379
def FeatureVendorXRivosVisni
1380-
: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">;
1380+
: RISCVExperimentalExtension<0, 1, "Rivos Vector Integer Small New">;
13811381
def HasVendorXRivosVisni
13821382
: Predicate<"Subtarget->hasVendorXRivosVisni()">,
13831383
AssemblerPredicate<(all_of FeatureVendorXRivosVisni),
1384-
"'XRivosVizisni' (Rivos Vector Small Integer New)">;
1384+
"'XRivosVisni' (Rivos Vector Integer Small New)">;
13851385

13861386
def FeatureVendorXRivosVizip
13871387
: RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;

llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos",
7676

7777
let isReMaterializable = 1, isAsCheapAsAMove = 1, vm = 0, vs2=0 in
7878
def RI_VZERO : RVInstV<0b000000, 0b00000, OPCFG, (outs VR:$vd),
79-
(ins), "ri.vzero", "$vd">;
79+
(ins), "ri.vzero.v", "$vd">;
8080

8181
let vm = 0, Constraints = "$vd = $vd_wb", RVVConstraint = NoConstraint in
8282
def RI_VINSERT : RVInstVXI<0b010000, OPMVX, (outs VR:$vd_wb),

llvm/test/MC/RISCV/xrivosvisni-valid.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,15 +9,15 @@
99
# RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111

12-
# CHECK-ASM-AND-OBJ: ri.vzero v1
12+
# CHECK-ASM-AND-OBJ: ri.vzero.v v1
1313
# CHECK-ASM: encoding: [0xdb,0x70,0x00,0x00]
14-
ri.vzero v1
15-
# CHECK-ASM-AND-OBJ: vzero v2
14+
ri.vzero.v v1
15+
# CHECK-ASM-AND-OBJ: ri.vzero.v v2
1616
# CHECK-ASM: encoding: [0x5b,0x71,0x00,0x00]
17-
ri.vzero v2
18-
# CHECK-ASM-AND-OBJ: vzero v3
17+
ri.vzero.v v2
18+
# CHECK-ASM-AND-OBJ: ri.vzero.v v3
1919
# CHECK-ASM: encoding: [0xdb,0x71,0x00,0x00]
20-
ri.vzero v3
20+
ri.vzero.v v3
2121

2222
# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v0, zero, 0
2323
# CHECK-ASM: encoding: [0x5b,0x60,0x00,0x40]

0 commit comments

Comments
 (0)