Add HasAVX10_2_512

Author: phoebewang

llvm/lib/Target/X86/X86InstrAMX.td

@@ -371,7 +371,7 @@ let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
 } // HasAMXTILE, HasAMXTRANSPOSE
 
 multiclass m_tcvtrowd2ps {
-  let Predicates = [HasAMXAVX512, In64BitMode] in {
+  let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {
     let SchedRW = [WriteSystem] in {
       def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
                     (ins TILE:$src1, i32u8imm:$src2),
@@ -382,12 +382,12 @@ multiclass m_tcvtrowd2ps {
                   "tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                   []>, T8,XS, EVEX, VVVV, EVEX_V512;
     }
-  } // HasAMXAVX512, In64BitMode
+  } // HasAMXAVX512, HasAVX10_2_512, In64BitMode
 }
 
 defm TCVTROWD2PS : m_tcvtrowd2ps;
 
-let Predicates = [HasAMXAVX512, In64BitMode] in {
+let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {
   let SchedRW = [WriteSystem] in {
     let  usesCustomInserter = 1 in {
       def PTCVTROWD2PSrri : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),
@@ -451,7 +451,7 @@ let Predicates = [HasAMXAVX512, In64BitMode] in {
 
 multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
                                 Prefix P1, Prefix P2> {
-  let Predicates = [HasAMXAVX512, In64BitMode], SchedRW = [WriteSystem] in {
+  let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode], SchedRW = [WriteSystem] in {
     let OpPrefix = P1 in
       def rre : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
                   (ins TILE:$src1, GR32:$src2),
@@ -490,7 +490,7 @@ multiclass m_tilemovrow {
                   "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                   []>, T8,PD, EVEX, VVVV, EVEX_V512;
     }
-  } // HasAMXAVX512, In64BitMode
+  } // HasAMXAVX512, HasAVX10_2_512, In64BitMode
 }
 
 defm TILEMOVROW : m_tilemovrow;