TableGen patterns give an obscure error when setting incorrect defs on an instruction that modifies physical registers

[JL2210]

Repro (run from build tree one level under project):

include "llvm/Target/Target.td"

def T : Target;

def A : Register<"">;
def B : Register<"">;

def R1 : RegisterClass<"", [i1], 0, (add B)>;
def R8 : RegisterClass<"", [i8], 0, (add A)>;

def FOO1 : Instruction {
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}

let Defs = [B] in
def FOO2 : Instruction {
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}

command:

./bin/llvm-tblgen -gen-global-isel -I ../llvm/include ./test.td

log:

Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
FOO2:   (FOO2:{ *:[i1] })
// record omitted for brevity
./test.td:18:5: error: Type set is empty for each HW mode in 'FOO2'
def FOO2 : Instruction {
    ^

[arsenm]

This isn't related to globalisel, this is the common pattern handling. You'll hit the same error in the DAG emitter too

[arsenm]

Version which doesn't hit another error:

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s

include "llvm/Target/Target.td"

def TestInstrInfo : InstrInfo;

def T : Target {
  let InstructionSet = TestInstrInfo;
}

def A : Register<"">;
def B : Register<"">;

def R1 : RegisterClass<"", [i1], 0, (add B)>;
def R8 : RegisterClass<"", [i8], 0, (add A)>;

def FOO1 : Instruction {
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}

def FOO2 : Instruction {
  let Uses = [B];
  let Defs = [B]; // No error without this
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}