[AArch64] atomic operations with syncscope::SingleThread conservatively lower to proper atomics

[gbaraldi]

I.e

define void @foo(ptr nonnull %myptr) {
top:
  store atomic i64 320, ptr %myptr syncscope("singlethread") release, align 8
  ret void
}

lowers to

_foo:                          ; @foo
        mov     w8, #320                        ; =0x140
        stlr    x8, [x0]
        ret

This seems pessimistic given that

define void @bar(ptr nonnull %myptr) {
top:
  store i64 320, ptr %myptr, align 8
  fence syncscope("singlethread") release
  ret void
}

Lowers to

_bar:                                   ; @bar
        mov     w8, #320                        ; =0x140
        str     x8, [x0]
        ret

I believe this requires a change in

llvm-project/llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines 2195 to 2204 in 8e61aaa

	if (SI->isAtomic()) {
	AtomicOrdering Ord = SI->getOrdering();
	// The non-atomic instructions are sufficient for relaxed stores.
	if (isReleaseOrStronger(Ord)) {
	// The STLR addressing mode only supports a base reg; pass that directly.
	Register AddrReg = getRegForValue(PtrV);
	return emitStoreRelease(VT, SrcReg, AddrReg,
	createMachineMemOperandFor(I));
	}
	}

but I'm not familiar enough with llvm backend specifics

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Gabriel Baraldi (gbaraldi)

I.e ```llvm define void @foo(ptr nonnull %myptr) { top: store atomic i64 320, ptr %myptr syncscope("singlethread") release, align 8 ret void } ``` lowers to ```s _foo: ; @foo mov w8, #320 ; =0x140 stlr x8, [x0] ret ```

This seems pessimistic given that

define void @<!-- -->bar(ptr nonnull %myptr) {
top:
  store i64 320, ptr %myptr, align 8
  fence syncscope("singlethread") release
  ret void
}

Lowers to

_bar:                                   ; @<!-- -->bar
        mov     w8, #<!-- -->320                        ; =0x140
        str     x8, [x0]
        ret

I believe this requires a change in

llvm-project/llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines 2195 to 2204 in 8e61aaa

	if (SI->isAtomic()) {
	AtomicOrdering Ord = SI->getOrdering();
	// The non-atomic instructions are sufficient for relaxed stores.
	if (isReleaseOrStronger(Ord)) {
	// The STLR addressing mode only supports a base reg; pass that directly.
	Register AddrReg = getRegForValue(PtrV);
	return emitStoreRelease(VT, SrcReg, AddrReg,
	createMachineMemOperandFor(I));
	}
	}

but I'm not familiar enough with llvm backend specifics