[RISCV][GISel] Add regbank and instruction selection tests for f16 load/store. NFC

[topperc]

The legalizer doesn't think these are legal yet so I had to disable the legality check.

[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

Author: Craig Topper (topperc)

Changes

The legalizer doesn't think these are legal yet so I had to disable the legality check.

---

Full diff: https://github.com/llvm/llvm-project/pull/116101.diff

2 Files Affected:

• (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir (+49-4)
• (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir (+54-4)

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
index 23640d39be4d33..5441d7c6673bc7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
@@ -1,8 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select %s -o - \
-# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select %s -o - \
-# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
+# RUN:   -disable-gisel-legality-check | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
+# RUN:   -disable-gisel-legality-check | FileCheck %s
 
 ---
 name:            fp_store_f32
@@ -93,3 +93,48 @@ body:             |
     PseudoRET implicit $f10_d
 
 ...
+---
+name:            fp_store_f16
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $f10_h
+
+    ; CHECK-LABEL: name: fp_store_f16
+    ; CHECK: liveins: $x10, $f10_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f10_h
+    ; CHECK-NEXT: FSH [[COPY1]], [[COPY]], 0 :: (store (s16))
+    ; CHECK-NEXT: PseudoRET
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s16) = COPY $f10_h
+    G_STORE %1(s16), %0(p0) :: (store (s16))
+    PseudoRET
+
+...
+---
+name:            fp_load_f16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: fp_load_f16
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[FLH:%[0-9]+]]:fpr16 = FLH [[COPY]], 0 :: (load (s16))
+    ; CHECK-NEXT: $f10_h = COPY [[FLH]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s16) = G_LOAD %0(p0) :: (load (s16))
+    $f10_h = COPY %1(s16)
+    PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
index 50a8faa2504f38..f74362298a6cb9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,9 +1,9 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
-# RUN:   -simplify-mir -verify-machineinstrs %s \
+# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
-# RUN:   -simplify-mir -verify-machineinstrs %s \
+# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck %s --check-prefixes=CHECK
 
 ---
@@ -150,3 +150,53 @@ body:             |
     PseudoRET implicit $f10_d
 
 ...
+---
+name:            fp_store_fp_def_f16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x10, $f10_h, $f11_h
+
+    ; CHECK-LABEL: name: fp_store_fp_def_f16
+    ; CHECK: liveins: $x10, $f10_h, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
+    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
+    ; CHECK-NEXT: PseudoRET
+    %0:_(p0) = COPY $x10
+    %1:_(s16) = COPY $f10_h
+    %2:_(s16) = COPY $f11_h
+    %3:_(s16) = G_FADD %1, %2
+    G_STORE %3(s16), %0(p0) :: (store (s16))
+    PseudoRET
+
+...
+---
+name:            fp_load_fp_use_f16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x10, $f10_h
+
+    ; CHECK-LABEL: name: fp_load_fp_use_f16
+    ; CHECK: liveins: $x10, $f10_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:_(p0) = COPY $x10
+    %1:_(s16) = COPY $f10_h
+    %2:_(s16) = G_LOAD %0(p0) :: (load (s16))
+    %3:_(s16) = G_FADD %2, %1
+    $f10_h = COPY %3(s16)
+    PseudoRET implicit $f10_h
+
+...