[AArch64] Failure to combine bitwise not of shift into `mvn`

[Kmeakin]

https://godbolt.org/z/7sKhdbr4E

The mvn (move-not) instruction produces the bitwise not of a shifted/rotated register. GCC recognizes this pattern and produces mvn, but clang does not

clang:

mvn_lsl_1_u8(unsigned char):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #1
        ret

mvn_lsl_1_u16(unsigned short):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #1
        ret

mvn_lsl_1_u32(unsigned int):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #1
        ret

mvn_lsl_1_u64(unsigned long):
        mov     x8, #-1
        eor     x0, x8, x0, lsl #1
        ret

GCC:

mvn_lsl_1_u8(unsigned char):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u16(unsigned short):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u32(unsigned int):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u64(unsigned long):
        mvn     x0, x0, lsl 1
        ret

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Karl Meakin (Kmeakin)

https://godbolt.org/z/7sKhdbr4E

The mvn (move-not) instruction produces the bitwise not of a shifted/rotated register. GCC recognizes this pattern and produces mvn, but clang does not

clang:

mvn_lsl_1_u8(unsigned char):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #<!-- -->1
        ret

mvn_lsl_1_u16(unsigned short):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #<!-- -->1
        ret

mvn_lsl_1_u32(unsigned int):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #<!-- -->1
        ret

mvn_lsl_1_u64(unsigned long):
        mov     x8, #-1
        eor     x0, x8, x0, lsl #<!-- -->1
        ret

GCC:

mvn_lsl_1_u8(unsigned char):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u16(unsigned short):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u32(unsigned int):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u64(unsigned long):
        mvn     x0, x0, lsl 1
        ret

[davemgreen]

I think this needs some new tablegen patterns, similar to those in

llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td

Line 2960 in ae6b4b2

def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;

but with shifts.

[arvganesh]

Hi, I'd like to submit a patch for this issue. Thanks!

In this instance, is the expected end behavior to match the GCC output?

[efriedma-quic]

Yes, we should match gcc output.