[RISCV] Add call preserved regmask to tail calls. #122181
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Every call should have regmask operand to indicate what is preserved. VirtRegRewriter uses this to tell MachineRegisterInfo what registers are used by a function. If the mask isn't present the registers potentially clobbered by a tail called function aren't counted. I have checked ARM, AArch64, and X86 and they all have a regmask operand on their tail calls. I believe thie fixes an issue I'm seeing with IPRA.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesEvery call should have regmask operand to indicate what registers are preserved or clobbered by the call. VirtRegRewriter uses this to tell MachineRegisterInfo what registers are clobbered by a function. If the mask isn't present the registers potentially clobbered by a tail called function aren't counted. I have checked ARM, AArch64, and X86 and they all have a regmask operand on their tail calls. I believe this fixes an issue I'm seeing with IPRA. Full diff: https://github.com/llvm/llvm-project/pull/122181.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2eeca45ac414bd..6c58989b1afb4c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20273,13 +20273,11 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
for (auto &Reg : RegsToPass)
Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
- if (!IsTailCall) {
- // Add a register mask operand representing the call-preserved registers.
- const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
- const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
- assert(Mask && "Missing call preserved mask for calling convention");
- Ops.push_back(DAG.getRegisterMask(Mask));
- }
+ // Add a register mask operand representing the call-preserved registers.
+ const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
+ const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
+ assert(Mask && "Missing call preserved mask for calling convention");
+ Ops.push_back(DAG.getRegisterMask(Mask));
// Glue the call to the argument copies, if any.
if (Glue.getNode())
diff --git a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
index 4c47b5f741fa67..2c428cf4ac87c6 100644
--- a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
+++ b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
@@ -20,7 +20,7 @@ define void @f2(ptr noundef %x) #0 {
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprtc = COPY $x10
- ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], implicit $x2, cfi-type 12345678
+ ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], csr_ilp32_lp64, implicit $x2, cfi-type 12345678
tail call void %x() [ "kcfi"(i32 12345678) ]
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/kcfi-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-mir.ll
index f9f383a35358c2..0c0d39a8bf87d3 100644
--- a/llvm/test/CodeGen/RISCV/kcfi-mir.ll
+++ b/llvm/test/CodeGen/RISCV/kcfi-mir.ll
@@ -30,7 +30,7 @@ define void @f2(ptr noundef %x) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $x6, implicit-def $x6_w, implicit-def $x6_h, implicit-def $x7, implicit-def $x7_w, implicit-def $x7_h, implicit-def $x28, implicit-def $x28_w, implicit-def $x28_h, implicit-def $x29, implicit-def $x29_w, implicit-def $x29_h, implicit-def $x30, implicit-def $x30_w, implicit-def $x30_h, implicit-def $x31, implicit-def $x31_w, implicit-def $x31_h, implicit killed $x10, implicit $x2 {
; CHECK-NEXT: KCFI_CHECK $x10, 12345678, implicit-def $x6, implicit-def $x7, implicit-def $x28, implicit-def $x29, implicit-def $x30, implicit-def $x31
- ; CHECK-NEXT: PseudoTAILIndirect killed $x10, implicit $x2
+ ; CHECK-NEXT: PseudoTAILIndirect killed $x10, csr_ilp32_lp64, implicit $x2
; CHECK-NEXT: }
tail call void %x() [ "kcfi"(i32 12345678) ]
ret void
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preames
approved these changes
Jan 8, 2025
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LGTM - Spot checked the x86 and AArch64 code, this looks reasonable.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/11397 Here is the relevant piece of the build log for the reference |
Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/108/builds/7896 Here is the relevant piece of the build log for the reference |
Contributor
Great! I checked that this can fix an issue I saw when I played around with IPRA as well! |
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Every call should have regmask operand to indicate what registers are preserved or clobbered by the call. VirtRegRewriter uses this to tell MachineRegisterInfo what registers are clobbered by a function. If the mask isn't present the registers potentially clobbered by a tail called function aren't counted. I have checked ARM, AArch64, and X86 and they all have a regmask operand on their tail calls.
I believe this fixes an issue I'm seeing with IPRA.