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@lenary lenary commented Jan 23, 2025

This was left over from 408659c.

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llvmbot commented Jan 23, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

This was left over from 408659c.


Full diff: https://github.com/llvm/llvm-project/pull/124202.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-2)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f7efd5f437fbb1..a2c1a986d4034f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21133,8 +21133,6 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       }
       break;
     case 'R':
-      if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
-        return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
       return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
     default:
       break;

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LGTM

@lenary lenary merged commit e06b703 into llvm:main Jan 24, 2025
10 checks passed
@lenary lenary deleted the pr/riscv-redundant-regclass branch January 24, 2025 01:40
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3 participants