s390x: `llvm.fshl.i128` is not optimized well

[folkertdev]

The llvm.fshl intrinsic is neat. Sadly, the s390x backend does not pick good instructions for it.

https://godbolt.org/z/j6Kcob8oa (or https://godbolt.org/z/eq7Gd4WKG for a pure LLVM IR example)

e.g. this LLVM IR

define noundef <16 x i8> @vec_sld_manual(<16 x i8> %a, <16 x i8> %b) unnamed_addr {
start:
  %0 = bitcast <16 x i8> %a to i128
  %1 = bitcast <16 x i8> %b to i128
  %_3 = tail call noundef i128 @llvm.fshl.i128(i128 noundef %0, i128 noundef %1, i128 noundef 32) #4
  %2 = bitcast i128 %_3 to <16 x i8>
  ret <16 x i8> %2
}

define <16 x i8> @vec_sld_builtin(<16 x i8> %a, <16 x i8> %b) unnamed_addr {
start:
  %_0 = tail call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 noundef 4) #4
  ret <16 x i8> %_0
}

declare i128 @llvm.fshl.i128(i128, i128, i128) unnamed_addr #2

declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32 immarg) unnamed_addr #3

A llvm.fshl.i128 with a compile-time known value that is a multiple of 8 can be lowered to a vsldb, but that does not happen

vec_sld_manual:
        vrepib  %v0, 96
        vsrlb   %v0, %v26, %v0
        vrepib  %v1, 32
        vslb    %v1, %v24, %v1
        vo      %v24, %v1, %v0
        br      %r14

vec_sld_builtin:
        vsldb   %v24, %v24, %v26, 4
        br      %r14

analogous simplifications are possible for vec_sldw and vec_sldb

[folkertdev]

and there is also llvm.fshr which could be used for vec_srdb

[folkertdev]

I think the fix works as intended, and does work for the left shifts, but in practice it does not for the right shifts because LLVM appears to prefer to rewrite them as fshl:

https://godbolt.org/z/ossMvr31E

define <16 x i8> @vec_sld_manual(<16 x i8> %a, <16 x i8> %b) unnamed_addr {
start:
  %0 = bitcast <16 x i8> %a to i128
  %1 = bitcast <16 x i8> %b to i128
  %_3 = tail call i128 @llvm.fshl.i128(i128 %0, i128 %1, i128 123)
  %2 = bitcast i128 %_3 to <16 x i8>
  ret <16 x i8> %2
}

define <16 x i8> @vec_sld_builtin(<16 x i8> %a, <16 x i8> %b) unnamed_addr {
start:
  %_0 = tail call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 noundef 5) #4
  ret <16 x i8> %_0
}

declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32 immarg) unnamed_addr #2

declare i128 @llvm.fshl.i128(i128, i128, i128) #3

resulting in

vec_sld_manual:
        vsldb   %v0, %v24, %v26, 15
        vsldb   %v1, %v26, %v26, 15
        vsld    %v24, %v0, %v1, 3
        br      %r14

vec_sld_builtin:
        vsrd    %v24, %v24, %v26, 5
        br      %r14

There may be a good reason for that in general, but here it means that the patterns from the fix don't apply. I think that an fshl by 128 - 8 .. 128 should be lowered to vsrd as well. (and the inverse as well perhaps? or maybe there is something more clever that LLVM can do to make fshl N == fshr (128 - N) % 128?)