[llvm] X86 backend ignores prefer-vector-width=256 and generates vmovaps with zmm registers

[ezhulenev]

Godbolt: https://godbolt.org/z/sx6bjjYYK

Function attribute is ignored and in the end LLVM generates avx512 movs. I'm still debugging this, but it crashes at run time because pointers are not 64 byte aligned, and I'm not sure how LLVM decide to use avx512 aligned movs

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Eugene Zhulenev (ezhulenev)

Godbolt: https://godbolt.org/z/sx6bjjYYK

Function attribute is ignored and in the end LLVM generates avx512 movs. I'm still debugging this, but it crashes at run time because pointers are not 64 byte aligned, and I'm not sure how LLVM decide to use avx512 aligned movs

[topperc]

There's a load <8 x i64>. That's a 512-bit vector. Prefer-vector-width won't change it. Prefer-vector-width is primarily for the autovectorizer.

Not sure about the alignment

[ezhulenev]

That is vmovups and I think it’s correct, the problem seems to be in vmovaps at line 19. It doesn’t correspond to any instruction in the original IR and makes alignment assumptions that I’m not sure are correct

[topperc]

That is vmovups and I think it’s correct, the problem seems to be in vmovaps at line 19. It doesn’t correspond to any instruction in the original IR and makes alignment assumptions that I’m not sure are correct

I believe its for the extractelt with the variable index. The vector is spilled to the stack and then the correct element is loaded with a scalar load. I believe these 2 instructions at the beginning aligned the stack pointer enough for this to be an aligned store.

        and     rsp, -64
        sub     rsp, 128