[RISCV] Correct disassembly of cm.push/pop for RVE. #133816
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
We shouldn't disassemble any encoding that refers to registers x16-x31 with RV32E.
Member
|
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesWe shouldn't disassemble any encoding that refers to registers x16-x31 with RV32E. Full diff: https://github.com/llvm/llvm-project/pull/133816.diff 5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b22a4a7246c23..d8fa12391692d 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -505,10 +505,10 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
const MCDisassembler *Decoder);
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder);
+ uint64_t Address, const MCDisassembler *Decoder);
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder);
+ uint64_t Address, const MCDisassembler *Decoder);
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
uint64_t Address, const void *Decoder);
@@ -618,16 +618,18 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
}
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder) {
- if (Imm < RISCVZC::RA)
+ uint64_t Address, const MCDisassembler *Decoder) {
+ bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
+ if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder) {
- if (Imm < RISCVZC::RA_S0)
+ uint64_t Address, const MCDisassembler *Decoder) {
+ bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
+ if (Imm < RISCVZC::RA_S0 || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
diff --git a/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s b/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s
new file mode 100644
index 0000000000000..6c3ef3000e77e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s
@@ -0,0 +1,21 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+e,+experimental-xqccmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xqccmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+experimental-xqccmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV32E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:19: error: invalid register
+qc.cm.push {ra,s0-s2}, -16
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: invalid register
+qc.cm.popret {ra,s0-s2}, 16
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+qc.cm.pop {x1, x8-x9, x18}, 16
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+qc.cm.pushfp {x1, x8-x9, x18}, -16
diff --git a/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s b/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s
new file mode 100644
index 0000000000000..eaf6b350c2341
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+e,+zcmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+zcmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV32E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.push {ra,s0-s2}, -16
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: invalid register
+cm.popret {ra,s0-s2}, 16
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+cm.pop {x1, x8-x9, x18}, 16
diff --git a/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s b/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s
new file mode 100644
index 0000000000000..f34ce83448070
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s
@@ -0,0 +1,21 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+e,+experimental-xqccmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+experimental-xqccmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV64E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:19: error: invalid register
+qc.cm.push {ra,s0-s2}, -32
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: invalid register
+qc.cm.popret {ra,s0-s2}, 32
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+qc.cm.pop {x1, x8-x9, x18}, 32
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+qc.cm.pushfp {x1, x8-x9, x18}, -32
diff --git a/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s b/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s
new file mode 100644
index 0000000000000..e99721d96a17c
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+e,+zcmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+zcmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV64E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.push {ra,s0-s2}, -32
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: invalid register
+cm.popret {ra,s0-s2}, 32
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+cm.pop {x1, x8-x9, x18}, 32
|
Member
|
@llvm/pr-subscribers-mc Author: Craig Topper (topperc) ChangesWe shouldn't disassemble any encoding that refers to registers x16-x31 with RV32E. Full diff: https://github.com/llvm/llvm-project/pull/133816.diff 5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b22a4a7246c23..d8fa12391692d 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -505,10 +505,10 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
const MCDisassembler *Decoder);
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder);
+ uint64_t Address, const MCDisassembler *Decoder);
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder);
+ uint64_t Address, const MCDisassembler *Decoder);
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
uint64_t Address, const void *Decoder);
@@ -618,16 +618,18 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
}
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder) {
- if (Imm < RISCVZC::RA)
+ uint64_t Address, const MCDisassembler *Decoder) {
+ bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
+ if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder) {
- if (Imm < RISCVZC::RA_S0)
+ uint64_t Address, const MCDisassembler *Decoder) {
+ bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
+ if (Imm < RISCVZC::RA_S0 || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
diff --git a/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s b/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s
new file mode 100644
index 0000000000000..6c3ef3000e77e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s
@@ -0,0 +1,21 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+e,+experimental-xqccmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xqccmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+experimental-xqccmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV32E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:19: error: invalid register
+qc.cm.push {ra,s0-s2}, -16
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: invalid register
+qc.cm.popret {ra,s0-s2}, 16
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+qc.cm.pop {x1, x8-x9, x18}, 16
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+qc.cm.pushfp {x1, x8-x9, x18}, -16
diff --git a/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s b/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s
new file mode 100644
index 0000000000000..eaf6b350c2341
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32e-zcmp-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+e,+zcmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+zcmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV32E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.push {ra,s0-s2}, -16
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: invalid register
+cm.popret {ra,s0-s2}, 16
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+cm.pop {x1, x8-x9, x18}, 16
diff --git a/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s b/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s
new file mode 100644
index 0000000000000..f34ce83448070
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s
@@ -0,0 +1,21 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+e,+experimental-xqccmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+experimental-xqccmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV64E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:19: error: invalid register
+qc.cm.push {ra,s0-s2}, -32
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: invalid register
+qc.cm.popret {ra,s0-s2}, 32
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
+qc.cm.pop {x1, x8-x9, x18}, 32
+# CHECK-DIS: b972 <unknown>
+# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
+qc.cm.pushfp {x1, x8-x9, x18}, -32
diff --git a/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s b/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s
new file mode 100644
index 0000000000000..e99721d96a17c
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64e-zcmp-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+e,+zcmp < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmp < %s \
+# RUN: | llvm-objdump --mattr=+e,+zcmp -M no-aliases -d -r - \
+# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+
+# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
+# are rejected for RV64E, when both assembling and disassembling.
+
+
+# CHECK-DIS: b872 <unknown>
+# CHECK: :[[@LINE+1]]:16: error: invalid register
+cm.push {ra,s0-s2}, -32
+# CHECK-DIS: be72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: invalid register
+cm.popret {ra,s0-s2}, 32
+# CHECK-DIS: ba72 <unknown>
+# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
+cm.pop {x1, x8-x9, x18}, 32
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
lenary
approved these changes
Apr 1, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
We shouldn't disassemble any encoding that refers to registers x16-x31 with RV32E.