[SPARC] Disassembler doesn't sign extend and aligns PC relative disponents.

[Rot127]

According to the SparcV9 ISA the branch instructions with the format 2-4 have displacement immediate values which get sign extended:

But the operand types for these displacement immediates never define a decoding method:

llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td

Lines 224 to 230 in 865fb9c

	def bprtarget : Operand<OtherVT> {
	let EncoderMethod = "getBranchPredTargetOpValue";
	}
	def bprtarget16 : Operand<OtherVT> {
	let EncoderMethod = "getBranchOnRegTargetOpValue";
	}

This leads to the bits being simply extracted and added as unsigned immediate operand to the MCInst.

The resulting branch instructions are not aligned, PC-relative or correctly sign extended values in the disassembler.

echo "0x10, 0xbf, 0xff, 0xff" | llvm-mc --triple=sparcv9 --disassemble
	.text
	ba 4194303 // = 0x3FFFFF but should be 0xffffffff_fffffffc

[brad0]

cc @koachan @MaskRay

[koachan]

This is probably related to #122196, will look into it.

[Rot127]

Yeah, looks like the same issue. Effected instruction classes are F2_4 (16bit imm), F2_3 (19bit imm), and F2_2 (22bit imm).

[Rot127]

@koachan I don't have time to port it to upstream LLVM unfortunately, but here is the fix for our use case you could use.

TableGen file: rizinorg@5e1b6dd

And the diff for the SparcDisassembler.cpp. It is C and not C++ because for Capstone we use C++ -> C translated LLVM disassemblers. Still straight forward to port. Although it might be better for the C++ case to use a template function.

diff --git a/arch/Sparc/SparcDisassembler.c b/arch/Sparc/SparcDisassembler.c
index 976a1aed..03b8c535 100644
--- a/arch/Sparc/SparcDisassembler.c
+++ b/arch/Sparc/SparcDisassembler.c
@@ -104,6 +104,33 @@ static const uint16_t CPPairDecoderTable[] = {
        Sparc_C24_C25, Sparc_C26_C27, Sparc_C28_C29, Sparc_C30_C31
 };
 
+static DecodeStatus DecodeDisp19(MCInst *Inst, uint32_t ImmVal,
+                                              uint64_t Address,
+                                              const void *Decoder)
+{
+       int64_t BranchTarget = Address + (SignExtend64(ImmVal, 19)) * 4);
+       MCOperand_CreateImm0(Inst, BranchTarget);
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDisp16(MCInst *Inst, uint32_t ImmVal,
+                                              uint64_t Address,
+                                              const void *Decoder)
+{
+       int64_t BranchTarget = Address + (SignExtend64(ImmVal, 16) * 4);
+       MCOperand_CreateImm0(Inst, BranchTarget);
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDisp22(MCInst *Inst, uint32_t ImmVal,
+                                              uint64_t Address,
+                                              const void *Decoder)
+{
+       int64_t BranchTarget = Address + (SignExtend64(ImmVal, 22) * 4);
+       MCOperand_CreateImm0(Inst, BranchTarget);
+       return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
                                               uint64_t Address,
                                               const void *Decoder)