Skip to content

[RISCV] Remove -O0 from rv32xandesperf.ll. NFC #154224

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Aug 18, 2025
Merged

[RISCV] Remove -O0 from rv32xandesperf.ll. NFC #154224

merged 1 commit into from
Aug 18, 2025

Conversation

@topperc
Copy link
Collaborator

@topperc topperc commented Aug 18, 2025

Adjust IR to make tests generate the expected branch instructions.

@topperc
[RISCV] Remove -O0 from rv32xandesperf.ll. NFC
65beb40 
Adjust IR to make tests generate the expected branch instructions.
@topperc topperc requested review from jrtc27 and lenary August 18, 2025 23:09
@llvmbot
Copy link
Member

llvmbot commented Aug 18, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

Adjust IR to make tests generate the expected branch instructions.

Full diff: https://github.com/llvm/llvm-project/pull/154224.diff

1 Files Affected:

  • (modified) llvm/test/CodeGen/RISCV/rv32xandesperf.ll (+33-73)
diff --git a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
index 6f1d168358e2e..85666f70ce535 100644
--- a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
+++ b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
 ; NDS.BBC
@@ -8,15 +8,14 @@ define i32 @bbc(i32 %a) nounwind {
 ; CHECK-LABEL: bbc:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.bbc a0, 16, .LBB0_2
-; CHECK-NEXT:    j .LBB0_1
-; CHECK-NEXT:  .LBB0_1: # %f
-; CHECK-NEXT:    li a0, 0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_2: # %t
+; CHECK-NEXT:  # %bb.1: # %t
 ; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: # %f
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
   %and = and i32 %a, 65536
-  %tst = icmp eq i32 %and, 0
+  %tst = icmp ne i32 %and, 0
   br i1 %tst, label %t, label %f
 f:
   ret i32 0
@@ -27,16 +26,11 @@ t:
 define i32 @select_bbc(i32 %a, i32 %b, i32 %c) nounwind {
 ; CHECK-LABEL: select_bbc:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sw a2, 8(sp) # 4-byte Folded Spill
-; CHECK-NEXT:    sw a1, 12(sp) # 4-byte Folded Spill
 ; CHECK-NEXT:    nds.bbc a0, 16, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a1, a2
 ; CHECK-NEXT:  .LBB1_2:
-; CHECK-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
   %and = and i32 %a, 65536
   %tst = icmp eq i32 %and, 0
@@ -50,15 +44,14 @@ define i32 @bbs(i32 %a) nounwind {
 ; CHECK-LABEL: bbs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.bbs a0, 16, .LBB2_2
-; CHECK-NEXT:    j .LBB2_1
-; CHECK-NEXT:  .LBB2_1: # %f
-; CHECK-NEXT:    li a0, 0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB2_2: # %t
+; CHECK-NEXT:  # %bb.1: # %t
 ; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB2_2: # %f
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
   %and = and i32 %a, 65536
-  %tst = icmp ne i32 %and, 0
+  %tst = icmp eq i32 %and, 0
   br i1 %tst, label %t, label %f
 f:
   ret i32 0
@@ -69,16 +62,11 @@ t:
 define i32 @select_bbs(i32 %a, i32 %b, i32 %c) nounwind {
 ; CHECK-LABEL: select_bbs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sw a2, 8(sp) # 4-byte Folded Spill
-; CHECK-NEXT:    sw a1, 12(sp) # 4-byte Folded Spill
 ; CHECK-NEXT:    nds.bbs a0, 16, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a1, a2
 ; CHECK-NEXT:  .LBB3_2:
-; CHECK-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
   %and = and i32 %a, 65536
   %tst = icmp ne i32 %and, 0
@@ -92,14 +80,13 @@ define i32 @beqc(i32 %a) nounwind {
 ; CHECK-LABEL: beqc:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.beqc a0, 5, .LBB4_2
-; CHECK-NEXT:    j .LBB4_1
-; CHECK-NEXT:  .LBB4_1: # %f
-; CHECK-NEXT:    li a0, 0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB4_2: # %t
+; CHECK-NEXT:  # %bb.1: # %t
 ; CHECK-NEXT:    li a0, 1
 ; CHECK-NEXT:    ret
-  %tst = icmp eq i32 %a, 5
+; CHECK-NEXT:  .LBB4_2: # %f
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %tst = icmp ne i32 %a, 5
   br i1 %tst, label %t, label %f
 f:
   ret i32 0
@@ -110,16 +97,11 @@ t:
 define i32 @select_beqc(i32 %a, i32 %b, i32 %c) nounwind {
 ; CHECK-LABEL: select_beqc:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sw a2, 8(sp) # 4-byte Folded Spill
-; CHECK-NEXT:    sw a1, 12(sp) # 4-byte Folded Spill
 ; CHECK-NEXT:    nds.beqc a0, 5, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a1, a2
 ; CHECK-NEXT:  .LBB5_2:
-; CHECK-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
   %tst = icmp eq i32 %a, 5
   %ret = select i1 %tst, i32 %b, i32 %c
@@ -132,14 +114,13 @@ define i32 @bnec(i32 %a) nounwind {
 ; CHECK-LABEL: bnec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.bnec a0, 5, .LBB6_2
-; CHECK-NEXT:    j .LBB6_1
-; CHECK-NEXT:  .LBB6_1: # %f
-; CHECK-NEXT:    li a0, 0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB6_2: # %t
+; CHECK-NEXT:  # %bb.1: # %t
 ; CHECK-NEXT:    li a0, 1
 ; CHECK-NEXT:    ret
-  %tst = icmp ne i32 %a, 5
+; CHECK-NEXT:  .LBB6_2: # %f
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %tst = icmp eq i32 %a, 5
   br i1 %tst, label %t, label %f
 f:
   ret i32 0
@@ -150,16 +131,11 @@ t:
 define i32 @select_bnec(i32 %a, i32 %b, i32 %c) nounwind {
 ; CHECK-LABEL: select_bnec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    sw a2, 8(sp) # 4-byte Folded Spill
-; CHECK-NEXT:    sw a1, 12(sp) # 4-byte Folded Spill
 ; CHECK-NEXT:    nds.bnec a0, 5, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a1, a2
 ; CHECK-NEXT:  .LBB7_2:
-; CHECK-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
   %tst = icmp ne i32 %a, 5
   %ret = select i1 %tst, i32 %b, i32 %c
@@ -182,7 +158,6 @@ define i32 @bfoz_from_and_i32(i32 %x) {
 define i64 @bfoz_from_and_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    ret
@@ -203,7 +178,6 @@ define i32 @bfoz_from_and_lshr_i32(i32 %x) {
 define i64 @bfoz_from_and_lshr_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_lshr_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x12 killed $x11
 ; CHECK-NEXT:    nds.bfoz a0, a1, 25, 14
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    ret
@@ -225,8 +199,6 @@ define i32 @bfoz_from_lshr_and_i32(i32 %x) {
 define i64 @bfoz_from_lshr_and_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_lshr_and_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x12 killed $x11
-; CHECK-NEXT:    # kill: def $x12 killed $x10
 ; CHECK-NEXT:    andi a1, a1, 15
 ; CHECK-NEXT:    srli a0, a0, 24
 ; CHECK-NEXT:    slli a1, a1, 8
@@ -299,7 +271,6 @@ define i32 @bfos_from_ashr_shl_i32(i32 %x) {
 define i32 @bfos_from_ashr_sexti8_i32(i8 %x) {
 ; CHECK-LABEL: bfos_from_ashr_sexti8_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 7, 5
 ; CHECK-NEXT:    ret
   %sext = sext i8 %x to i32
@@ -310,7 +281,6 @@ define i32 @bfos_from_ashr_sexti8_i32(i8 %x) {
 define i32 @bfos_from_ashr_sexti16_i32(i16 %x) {
 ; CHECK-LABEL: bfos_from_ashr_sexti16_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 15, 11
 ; CHECK-NEXT:    ret
   %sext = sext i16 %x to i32
@@ -357,7 +327,6 @@ define i32 @sexti1_i32(i32 %a) {
 define i32 @sexti1_i32_2(i1 %a) {
 ; CHECK-LABEL: sexti1_i32_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 0, 0
 ; CHECK-NEXT:    ret
   %1 = sext i1 %a to i32
@@ -390,7 +359,6 @@ define i32 @sexti8_i32(i32 %a) {
 define i32 @sexti8_i32_2(i8 %a) {
 ; CHECK-LABEL: sexti8_i32_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 7, 0
 ; CHECK-NEXT:    ret
   %1 = sext i8 %a to i32
@@ -410,7 +378,6 @@ define i32 @sexti16_i32(i32 %a) {
 define i32 @sexti16_i32_2(i16 %a) {
 ; CHECK-LABEL: sexti16_i32_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 15, 0
 ; CHECK-NEXT:    ret
   %1 = sext i16 %a to i32
@@ -420,9 +387,8 @@ define i32 @sexti16_i32_2(i16 %a) {
 define i64 @sexti1_i64(i64 %a) {
 ; CHECK-LABEL: sexti1_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
-; CHECK-NEXT:    nds.bfos a1, a0, 0, 0
-; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    nds.bfos a0, a0, 0, 0
+; CHECK-NEXT:    mv a1, a0
 ; CHECK-NEXT:    ret
   %shl = shl i64 %a, 63
   %shr = ashr exact i64 %shl, 63
@@ -432,9 +398,8 @@ define i64 @sexti1_i64(i64 %a) {
 define i64 @sexti1_i64_2(i1 %a) {
 ; CHECK-LABEL: sexti1_i64_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
-; CHECK-NEXT:    nds.bfos a1, a0, 0, 0
-; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    nds.bfos a0, a0, 0, 0
+; CHECK-NEXT:    mv a1, a0
 ; CHECK-NEXT:    ret
   %1 = sext i1 %a to i64
   ret i64 %1
@@ -443,7 +408,6 @@ define i64 @sexti1_i64_2(i1 %a) {
 define i64 @sexti8_i64(i64 %a) {
 ; CHECK-LABEL: sexti8_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 7, 0
 ; CHECK-NEXT:    srai a1, a0, 31
 ; CHECK-NEXT:    ret
@@ -455,7 +419,6 @@ define i64 @sexti8_i64(i64 %a) {
 define i64 @sexti8_i64_2(i8 %a) {
 ; CHECK-LABEL: sexti8_i64_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 7, 0
 ; CHECK-NEXT:    srai a1, a0, 31
 ; CHECK-NEXT:    ret
@@ -466,7 +429,6 @@ define i64 @sexti8_i64_2(i8 %a) {
 define i64 @sexti16_i64(i64 %a) {
 ; CHECK-LABEL: sexti16_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 15, 0
 ; CHECK-NEXT:    srai a1, a0, 31
 ; CHECK-NEXT:    ret
@@ -478,7 +440,6 @@ define i64 @sexti16_i64(i64 %a) {
 define i64 @sexti16_i64_2(i16 %a) {
 ; CHECK-LABEL: sexti16_i64_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    nds.bfos a0, a0, 15, 0
 ; CHECK-NEXT:    srai a1, a0, 31
 ; CHECK-NEXT:    ret
@@ -489,7 +450,6 @@ define i64 @sexti16_i64_2(i16 %a) {
 define i64 @sexti32_i64(i64 %a) {
 ; CHECK-LABEL: sexti32_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $x11 killed $x10
 ; CHECK-NEXT:    srai a1, a0, 31
 ; CHECK-NEXT:    ret
   %shl = shl i64 %a, 32

lenary
lenary approved these changes Aug 18, 2025
View reviewed changes
Copy link
Member

@lenary lenary left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

jrtc27
jrtc27 approved these changes Aug 18, 2025
View reviewed changes
Copy link
Collaborator

@jrtc27 jrtc27 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Presumably the icmps you flipped were because otherwise bbc would give bbs and vice-versa due to basic block reordering?

@topperc
Copy link
Collaborator Author

topperc commented Aug 18, 2025

Presumably the icmps you flipped were because otherwise bbc would give bbs and vice-versa due to basic block reordering?

Exactly

@topperc topperc merged commit 396dfdf into llvm:main Aug 18, 2025
11 checks passed
@topperc topperc deleted the pr/xandesperf-test branch August 18, 2025 23:56
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@lenary lenary lenary approved these changes

@jrtc27 jrtc27 jrtc27 approved these changes

Assignees

No one assigned

Labels

backend:RISC-V

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

4 participants

@topperc @llvmbot @lenary @jrtc27