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[AArch64] AND optimization does not work if there is a freeze between AND and the cmp #154387

@AZero13

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@AZero13

Here is a case from the real world where this happens:

define i1 @test_disjoint(i1 %0, i32 %1, i32 %2) {
  %3 = or disjoint i32 %2, 8388608
  %4 = shl nuw i32 1, %1
  %5 = and i32 %3, %4
  %6 = icmp eq i32 %5, 0
  %7 = select i1 %0, i1 true, i1 %6
  ret i1 %7
}

We get:

test_disjoint:                          // @test_disjoint
        mov     w8, #1                          // =0x1
        orr     w9, w2, #0x800000
        lsl     w8, w8, w1
        and     w8, w9, w8
        cmp     w8, #0
        cset    w8, eq
        orr     w8, w0, w8
        and     w0, w8, #0x1
        ret

There are many ways to solve this problem.

In the short term, I guess we can fix this by special casing it. However, I am not sure of if this will be safe every time.

In all honesty, I think that perhaps this optimization should not be done at all in the long term. Why? This seems more like a peephole optimizer job.

So, my solution to this problem, and yes this definitely will not catch all cases because this works on a different domain to the SelDAG, is #153608, but also we don't do the replace all users in GISel anyway, so this benefits that too.

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