[AMDGPU] Hit an ICE with this message: `Cannot scavenge register in FI elimination!`

[Saldivarcher]

Here is the reproducer: https://godbolt.org/z/aP1oTbv7T

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Miguel Saldivar (Saldivarcher)

Here is the reproducer: https://godbolt.org/z/aP1oTbv7T

[arsenm]

More reduced:

target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"

define amdgpu_kernel void @issue155902(i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15, i64 %arg16, i64 %arg17, i64 %arg18, i64 %arg19, i64 %arg20, i64 %arg21, i64 %arg22, i64 %arg23, i64 %arg24, i64 %arg25, i64 %arg26, i64 %arg27, i64 %arg28, i64 %arg29, i64 %arg30, i64 %arg31, i64 %arg32, i64 %arg33, i64 %arg1, i64 %arg35, i64 %arg34, i64 %arg, i64 %arg38, i64 %arg39, i64 %arg40, i64 %arg41, i64 %arg42, i64 %arg43, i64 %arg44, i64 %arg37, i64 %arg46, i64 %arg47, i64 %arg48, i64 %arg49, i64 %arg45, i64 %arg36) {
bb:
  %alloca.big = alloca [4096 x i32], align 4, addrspace(5)
  %alloca304 = alloca [2 x i64], align 8, addrspace(5)
  %alloca307 = alloca i64, align 8, addrspace(5)
  store [2 x i64] zeroinitializer, ptr addrspace(5) %alloca304, align 8
  store i64 0, ptr addrspace(5) %alloca307, align 8
  store i64 %arg2, ptr addrspace(5) null, align 8
  store i64 %arg3, ptr addrspace(5) null, align 8
  store i64 %arg4, ptr addrspace(5) null, align 8
  store i64 %arg5, ptr addrspace(5) null, align 8
  store i64 %arg6, ptr addrspace(5) null, align 8
  store i64 %arg7, ptr addrspace(5) null, align 8
  store i64 %arg8, ptr addrspace(5) null, align 8
  store i64 %arg9, ptr addrspace(5) null, align 8
  store i64 %arg10, ptr addrspace(5) null, align 8
  store i64 %arg11, ptr addrspace(5) null, align 8
  store i64 %arg12, ptr addrspace(5) null, align 8
  store i64 %arg13, ptr addrspace(5) null, align 8
  store i64 %arg14, ptr addrspace(5) null, align 8
  store i64 %arg15, ptr addrspace(5) null, align 8
  store i64 %arg16, ptr addrspace(5) null, align 8
  store i64 %arg17, ptr addrspace(5) null, align 8
  store i64 %arg18, ptr addrspace(5) null, align 8
  store i64 %arg19, ptr addrspace(5) null, align 8
  store i64 %arg20, ptr addrspace(5) null, align 8
  store i64 %arg21, ptr addrspace(5) null, align 8
  store i64 %arg22, ptr addrspace(5) null, align 8
  store i64 %arg23, ptr addrspace(5) null, align 8
  store i64 %arg24, ptr addrspace(5) null, align 8
  store i64 %arg25, ptr addrspace(5) null, align 8
  store i64 %arg26, ptr addrspace(5) null, align 8
  store i64 %arg27, ptr addrspace(5) null, align 8
  store i64 %arg28, ptr addrspace(5) null, align 8
  store i64 %arg29, ptr addrspace(5) null, align 8
  store i64 %arg30, ptr addrspace(5) null, align 8
  store i64 %arg31, ptr addrspace(5) null, align 8
  store i64 %arg32, ptr addrspace(5) null, align 8
  store i64 %arg33, ptr addrspace(5) null, align 8
  store i64 %arg1, ptr addrspace(5) null, align 8
  store i64 %arg35, ptr addrspace(5) null, align 8
  store i64 %arg34, ptr addrspace(5) null, align 8
  store i64 %arg, ptr addrspace(5) null, align 8
  store i64 %arg38, ptr addrspace(5) null, align 8
  store i64 %arg39, ptr addrspace(5) null, align 8
  store i64 %arg40, ptr addrspace(5) null, align 8
  store i64 %arg41, ptr addrspace(5) null, align 8
  store i64 %arg42, ptr addrspace(5) null, align 8
  store i64 %arg43, ptr addrspace(5) null, align 8
  store i64 %arg44, ptr addrspace(5) null, align 8
  store i64 %arg37, ptr addrspace(5) null, align 8
  store i64 %arg46, ptr addrspace(5) null, align 8
  store i64 %arg47, ptr addrspace(5) null, align 8
  store i64 %arg48, ptr addrspace(5) null, align 8
  store i64 %arg49, ptr addrspace(5) null, align 8
  store i64 %arg45, ptr addrspace(5) null, align 8
  store i64 %arg36, ptr addrspace(5) null, align 8
  ret void
}

[arsenm]

WIP Patch: 0001-WIP-AMDGPU-Replace-scratch-store-with-vaddr-form-if-.patch

[arsenm]

This can also be worked around by adding the "frame-pointer"="all" attribute

[arsenm]

Another simpler fix we could try is to force an FP in kernels, if the stack frame is large enough that there could be an offset larger than the addressing mode limit