[RISCV] Suboptimal code generation for LMBench `rd`

[wangpc-pp]

See: https://godbolt.org/z/Wh3sW57qa

There are two problems:

1. Do we estimate the cost of gather/scatter too low? Because AArch64 won't vectorize this loop and the RISC-V GCC does the same.

<source>:35:6: remark: the cost-model indicates that vectorization is not beneficial [-Rpass-missed=loop-vectorize]
   35 |             while (p <= lastone) {
      |             ^
<source>:35:6: remark: the cost-model indicates that interleaving is not beneficial [-Rpass-missed=loop-vectorize]

2. Can we combine the loads before LoopVectorizer? As you can see, if we disable LV, then SLP will kick in and generate a better code seemingly.

.LBB0_5:
        vsetvli zero, a4, e32, m8, ta, ma
        vlse32.v        v8, (a2), a5
        vmv.s.x v16, a1
        vredsum.vs      v8, v8, v16
        addi    a2, a2, 512
        vmv.x.s a1, v8
        bgeu    a3, a2, .LBB0_5
        bnez    a0, .LBB0_4
        mv      a0, a1
        tail    use_int

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

See: https://godbolt.org/z/Wh3sW57qa

There are two problems:

1. Do we estimate the cost of gather/scatter too low? Because AArch64 won't vectorize this loop and the RISC-V GCC does the same.

<source>:35:6: remark: the cost-model indicates that vectorization is not beneficial [-Rpass-missed=loop-vectorize]
   35 |             while (p <= lastone) {
      |             ^
<source>:35:6: remark: the cost-model indicates that interleaving is not beneficial [-Rpass-missed=loop-vectorize]

2. Can we combine the loads before LoopVectorizer? As you can see, if we disable LV, then SLP will kick in and generate a better code seemingly.

.LBB0_5:
        vsetvli zero, a4, e32, m8, ta, ma
        vlse32.v        v8, (a2), a5
        vmv.s.x v16, a1
        vredsum.vs      v8, v8, v16
        addi    a2, a2, 512
        vmv.x.s a1, v8
        bgeu    a3, a2, .LBB0_5
        bnez    a0, .LBB0_4
        mv      a0, a1
        tail    use_int

[topperc]

Can we combine the loads before LoopVectorizer? As you can see, if we disable LV, then SLP will kick in and generate a better code seemingly.

The loop contains multiple scalar loads. The loop vectorizer will vectorize each one by using elements from future iterations of the scalar loop. SLP combines all of the loads from a single iteration of the loop.

[ElvisWang123]

My patch to increase gather/scatter cost #156386 (8fdae0c) relanded after the version of the trunk (e8b5fbd).
Will take a look if the loop still be vectorized after new trunk.

[wangpc-pp]

My patch to increase gather/scatter cost #156386 (8fdae0c) relanded after the version of the trunk (e8b5fbd). Will take a look if the loop still be vectorized after new trunk.

I just checked this, we still vectorize this loop with the latest trunk compiler. The cost increases a little bit but it is still smaller than the scalar loop.

[wangpc-pp]

Can we combine the loads before LoopVectorizer? As you can see, if we disable LV, then SLP will kick in and generate a better code seemingly.

The loop contains multiple scalar loads. The loop vectorizer will vectorize each one by using elements from future iterations of the scalar loop. SLP combines all of the loads from a single iteration of the loop.

Thanks! This is also my understanding. I just wonder if we can do SLP before LV, or, if current SLP implementation can combine all the vector operations after LV?

[arcbbb]

Thanks! This is also my understanding. I just wonder if we can do SLP before LV, or, if current SLP implementation can combine all the vector operations after LV?

The ordering can be case‑dependent. Sometimes LV→SLP wins, sometimes SLP→LV. I thought the ideal path is a VPlan‑based SLP that we could cost both and pick the winner.

[arcbbb]

See: https://godbolt.org/z/Wh3sW57qa

There are two problems:

1. Do we estimate the cost of gather/scatter too low? Because AArch64 won't vectorize this loop and the RISC-V GCC does the same.

:35:6: remark: the cost-model indicates that vectorization is not beneficial [-Rpass-missed=loop-vectorize] 35 | while (p <= lastone) { | ^ :35:6: remark: the cost-model indicates that interleaving is not beneficial [-Rpass-missed=loop-vectorize] 2. Can we combine the loads before LoopVectorizer? As you can see, if we disable LV, then SLP will kick in and generate a better code seemingly.

.LBB0_5:
vsetvli zero, a4, e32, m8, ta, ma
vlse32.v v8, (a2), a5
vmv.s.x v16, a1
vredsum.vs v8, v8, v16
addi a2, a2, 512
vmv.x.s a1, v8
bgeu a3, a2, .LBB0_5
bnez a0, .LBB0_4
mv a0, a1
tail use_int

looks like this is fixed in trunk.

[wangpc-pp]

looks like this is fixed in trunk.

Yeah! But which commit does this?