[RISCV] Reg allocation cause sub-optimal result

[zzzhhhl]

To allocate register for case below:

624B	  %29:gprnox0 = PseudoVSETVLI %55:gprnox0, 211, implicit-def dead $vl, implicit-def dead $vtype
640B	  %30:vrm8 = PseudoVLE32_V_M8 undef %30:vrm8(tied-def 0), %53:gpr, %29:gprnox0, 5, 2 :: (load unknown-size from %ir.in.addr.041, align 4)
656B	  %31:vrm8 = PseudoVLE32_V_M8 undef %31:vrm8(tied-def 0), %54:gpr, %29:gprnox0, 5, 2 :: (load unknown-size from %ir.other.addr.040, align 4)
672B	  %41:vrm8nov0 = nofpexcept PseudoVFDIV_VV_M8_E32 undef %41:vrm8nov0(tied-def 0), %30:vrm8, %31:vrm8, 7, %29:gprnox0, 5, 0, implicit $frm
688B	  early-clobber %35:vr = nofpexcept PseudoVMFLT_VFPR32_M8 %41:vrm8nov0, %34:fpr32, %29:gprnox0, 5
704B	  early-clobber %38:vr = nofpexcept PseudoVMFGT_VFPR32_M8 %41:vrm8nov0, %37:fpr32, %29:gprnox0, 5
720B	  %39:vr = PseudoVMAND_MM_M2 %35:vr, %38:vr, %29:gprnox0, 0
736B	  %40:vrm8 = nofpexcept PseudoVFCVT_RTZ_X_F_V_M8 undef %40:vrm8(tied-def 0), %41:vrm8nov0, %29:gprnox0, 5, 0
752B	  $v0 = COPY %39:vr
784B	  %41:vrm8nov0 = nofpexcept PseudoVFCVT_F_X_V_M8_E32_MASK %41:vrm8nov0(tied-def 0), %40:vrm8, killed $v0, 7, %29:gprnox0, 5, 1, implicit $frm
800B	  %43:vrm8 = nofpexcept PseudoVFMUL_VV_M8_E32 undef %43:vrm8(tied-def 0), %41:vrm8nov0, %31:vrm8, 7, %29:gprnox0, 5, 0, implicit $frm
816B	  %44:vrm8 = nofpexcept PseudoVFSUB_VV_M8_E32 undef %44:vrm8(tied-def 0), %30:vrm8, %43:vrm8, 7, %29:gprnox0, 5, 0, implicit $frm
832B	  PseudoVSE32_V_M8 %44:vrm8, %52:gpr, %29:gprnox0, 5 :: (store unknown-size into %ir.out.addr.042, align 4)
848B	  %53:gpr = SH2ADD %29:gprnox0, %53:gpr

For 736B, before allocating %40, all vrm8 register class is running out(except v0-v7). So when allocating %40, because of some strategy of greedy allocation, assuming it evict %30 ,and then assign v8m8(allocating to %30 before) to %40. and then push %30 into queue. But for %40, between def (736B)and use(784B), there is no overlap for v8m8. so this spill/reload is redundant. For now, i add a pass to eliminate this scenario at post-ra stage.

Is there any better solution?

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: None (zzzhhhl)

To allocate register for case below:

<img width="1900" height="968" alt="Image" src="https://github.com/user-attachments/assets/e10300a4-dec8-454d-b102-c1d5e05ebfef" />

For line 14110, before allocating %40, all vrm8 register class is running out(except v0-v7). So when allocating %40, because of some strategy of greedy allocation, assuming it evict %30 ,and then assign v8m8(allocating to %30 before) to %40. and then push %30 into queue. But for %40, between def (line 14110 )and use(line 14112), there is no overlap for v8m8. so this spill/reload is redundant. For now, i add a pass to eliminate this scenario at post-ra stage.

Is there any better solution?

[EugeneZelenko]

@zzzhhhl: Please use text snippets instead of screenshots. They are also searchable.

[zzzhhhl]

@zzzhhhl: Please use text snippets instead of screenshots. They are also searchable.

OK.

[preames]

Without a reproducer, it's hard to say much concretely, but I think you're running into a side effect of how the V0 mask is populated. @lukel97 had been working on moving the V0 copy insertion later and later in the pipeline, not sure where the status of that is right now, and whether that might help your example.

[zzzhhhl]

Without a reproducer, it's hard to say much concretely, but I think you're running into a side effect of how the V0 mask is populated. @lukel97 had been working on moving the V0 copy insertion later and later in the pipeline, not sure where the status of that is right now, and whether that might help your example.

COPY is not the matter. Using other code patch like a if-else branch(scalar) to replace COPY , it also reproduced.

[zzzhhhl]

@wangpc-pp could you have a see on this issue? except adding a pass, i have an idea to set %40 weight to inf to evict other assigned phy reg.

[wangpc-pp]

@wangpc-pp could you have a see on this issue? except adding a pass, i have an idea to set %40 weight to inf to evict other assigned phy reg.

I'd like to, but please provide a reduced reproducer first so that we can trace the compile log.

[zzzhhhl]

@wangpc-pp https://godbolt.org/
something different with our result because of clang version, but the link have redundant vs8r and vl8r.

[wangpc-pp]

@wangpc-pp https://godbolt.org/ something different with our result because of clang version, but the link have redundant vs8r and vl8r.

The link is broken.

[zzzhhhl]

#include <iostream>
#include <vector>
#include <cstddef>
#include <riscv_vector.h>
#include<math.h>

void test(float* out, float* in, float* other, int n, int *m, int c) {
  const int32_t int32_max = 0x7fffffff;
  const int32_t int32_min = 0x80000000;
  unsigned int l;
  vfloat32m8_t va, vb, vq, vt, vo;
  vint32m8_t vi;
  for (; n > 0; n -= l) {
    l = __riscv_vsetvl_e32m8(n);
    va = __riscv_vle32_v_f32m8(in, l);
    vb = __riscv_vle32_v_f32m8(other, l);

    vq = __riscv_vfdiv_vv_f32m8(va, vb, l);
    
    vbool4_t m0 = __riscv_vmflt_vf_f32m8_b4(vq, (float)int32_max, l);
    vbool4_t m1 = __riscv_vmfgt_vf_f32m8_b4(vq, (float)int32_min, l);
    vbool4_t m2 = __riscv_vmand_mm_b4(m0, m1, l);
    vi = __riscv_vfcvt_rtz_x_f_v_i32m8(vq, l);
    vt = __riscv_vfcvt_f_x_v_f32m8(vi, l);       
    vt = __riscv_vmerge_vvm_f32m8(vq, vt, m2, l);
    // remainder
    vt = __riscv_vfmul_vv_f32m8(vt, vb, l);
    vo = __riscv_vfsub_vv_f32m8(va, vt, l);

    __riscv_vse32_v_f32m8(out, vo, l);
    in += l;
    other += l;
    out += l;
  }
}

with compile option "-I/usr/local/ -march=rv64gcv -O2"
@wangpc-pp gcc has better result.

[wangpc-pp]

I don't know if there is something I missed, but I I think both GCC and LLVM will generate a spill and reload: https://godbolt.org/z/18vKdxzj1.