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Description
This commit c9821ab introduced a change to mitigate some edge cases when linked with MS CRT code by emitting a dmb ish post instruction to force a memory fence / barrier around the atomic operation.
So using clang 21.1.2, when I compile my little app:
int main()
{
int i = 6;
__atomic_fetch_add(&i, 2, __ATOMIC_SEQ_CST);
}
By default clang-cl generates armv8.0 instructions which look like this:
ldaxr w9,[x8]
add w9, w9, #2
stlxr w10, w9, [x8]
cbnz w10, main+20h
dmb ish
ldr x8, [sp,#8]
adrp x9,__security_cookie
ldr x9, [x9]
cmp x9, x8
bne main+58h
If I switch to arm8.1 (using option -mcpu=cortex-a76 in my test) then the instructions are these:
ldaddal w9, w8, [x8]
dmb ish
In this instance the dmb ish is redundant because the ldaddal is enforcing the memory order already.