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@XiaShark XiaShark commented Oct 13, 2025

I encountered a compilation crash issue, and after analysis, it was caused by the AArch64PostCoalescerPass, see https://godbolt.org/z/vPeqeo5Pa.
When replacing the register, if the source register has undef flag, we should propagate the flag to all uses of the destination register.

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llvmbot commented Oct 13, 2025

@llvm/pr-subscribers-backend-aarch64

Author: None (XiaShark)

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I encountered a compilation crash issue, and after analysis, it was caused by the AArch64PostCoalescerPass, see https://godbolt.org/z/vPeqeo5Pa.
If the destination register still has active uses, removing COALESCER_BARRIER is unsafe.


Full diff: https://github.com/llvm/llvm-project/pull/163119.diff

2 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp (+2)
  • (added) llvm/test/CodeGen/AArch64/aarch64-post-coalescer.ll (+14)
diff --git a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
index cdf2822f3ed9d..a8cb1eb07003f 100644
--- a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
@@ -72,6 +72,8 @@ bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
       case AArch64::COALESCER_BARRIER_FPR128: {
         Register Src = MI.getOperand(1).getReg();
         Register Dst = MI.getOperand(0).getReg();
+        if (MRI->hasOneDef(Dst) && !MRI->use_empty(Dst))
+          continue;
         if (Src != Dst)
           MRI->replaceRegWith(Dst, Src);
 
diff --git a/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.ll b/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.ll
new file mode 100644
index 0000000000000..adf6c72f9fb2f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=aarch64 -mattr=+sme -stop-ater=aarch64-post-coalescer-pass < %s | FileCheck %s
+
+; CHECK-LABEL: name: bar
+; CHECK: [[dst:%[0-9]+]]:fpr64 = COALESCER_BARRIER_FPR64 undef [[src:%[0-9]+]]
+
+target triple = "aarch64"
+
+declare void @foo(double) "aarch64_pstate_sm_enabled"
+
+define dso_local void @bar(double noundef %a) local_unnamed_addr {
+entry:
+  tail call void @foo(double poison) "aarch64_pstate_sm_enabled"
+  ret void
+}
\ No newline at end of file

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@sdesmalen-arm

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github-actions bot commented Oct 13, 2025

✅ With the latest revision this PR passed the undef deprecator.

@XiaShark XiaShark force-pushed the fix-post-coalescer-pass branch from 31a571b to 2a63b96 Compare October 14, 2025 03:08
@XiaShark XiaShark changed the title [AArch64PostCoalescer] Preserve COALESCER_BARRIER for active register uses [AArch64PostCoalescer] Propagate undef flag after replacing Oct 14, 2025
@XiaShark XiaShark force-pushed the fix-post-coalescer-pass branch from 2a63b96 to 4a67118 Compare October 14, 2025 09:14
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github-actions bot commented Oct 14, 2025

✅ With the latest revision this PR passed the C/C++ code formatter.

@XiaShark XiaShark force-pushed the fix-post-coalescer-pass branch from 4a67118 to 46112c5 Compare October 14, 2025 09:36
@XiaShark XiaShark force-pushed the fix-post-coalescer-pass branch 2 times, most recently from 6169d9a to 34bd13e Compare October 14, 2025 12:22
; CHECK-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-NEXT: RET_ReallyLR
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%1:fpr64 = COALESCER_BARRIER_FPR64 undef %1
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nit: would it be sufficient to test only for:

%1:fpr64 = COALESCER_BARRIER_FPR64 undef %1
$d0 = COPY %1
FAKE_USE implicit $d0

without the other machine instructions?

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It's fine, modified

… to MIR

This patch adds serialization of
AArch64FunctionInfo::HasStreamingModeChanges into MIR.
When replacing the register, if the source register has undef flag, we
should propagate the flag to all uses of the destination register.
@XiaShark XiaShark force-pushed the fix-post-coalescer-pass branch from 34bd13e to f8d19b8 Compare October 15, 2025 01:26
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LGTM, thank you!

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LGTM! Would you like us to merge this now?

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LGTM! Would you like us to merge this now?

Sure, thanks!

@MacDue MacDue merged commit 7f7f249 into llvm:main Oct 15, 2025
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