[X86] Failure to fold or disjoint nodes into a AVX512 predicated add instruction

[RKSimon]

https://gcc.godbolt.org/z/63scvzTGT

define <64 x i8> @select_add(<64 x i8> %0, <64 x i8> %1) {
  %add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65>
  %add1 = add <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
  %icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26>
  %res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0
  ret <64 x i8> %res
}

define <64 x i8> @select_or(<64 x i8> %0, <64 x i8> %1) {
  %add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65>
  %add1 = or disjoint <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
  %icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26>
  %res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0
  ret <64 x i8> %res
}

While the select_add case correctly folds an add into a predicated instruction:

select_add: # @select_add
  vpaddb .LCPI0_0(%rip), %zmm0, %zmm0
  vpcmpltub .LCPI0_1(%rip), %zmm0, %k1
  vpaddb .LCPI0_2(%rip), %zmm1, %zmm0 {%k1}
  retq

Using an add-like or-disjoint node fails to fold into the same add predicated instruction:

select_or: # @select_or
  vpaddb .LCPI1_0(%rip), %zmm0, %zmm0
  vpord .LCPI1_3(%rip){1to16}, %zmm1, %zmm1
  vpcmpltub .LCPI1_2(%rip), %zmm0, %k1
  vmovdqu8 %zmm1, %zmm0 {%k1}
  retq

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

https://gcc.godbolt.org/z/63scvzTGT ```ll define <64 x i8> @select_add(<64 x i8> %0, <64 x i8> %1) { %add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65> %add1 = add <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32> %icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26> %res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0 ret <64 x i8> %res }

define <64 x i8> @select_or(<64 x i8> %0, <64 x i8> %1) {
%add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65>
%add1 = or disjoint <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
%icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26>
%res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0
ret <64 x i8> %res
}

While the select_add case correctly folds an add into a predicated instruction:
```s
select_add: # @<!-- -->select_add
  vpaddb .LCPI0_0(%rip), %zmm0, %zmm0
  vpcmpltub .LCPI0_1(%rip), %zmm0, %k1
  vpaddb .LCPI0_2(%rip), %zmm1, %zmm0 {%k1}
  retq

Using an add-like or-disjoint node fails to folds into the same add predicated instruction:

select_or: # @<!-- -->select_or
  vpaddb .LCPI1_0(%rip), %zmm0, %zmm0
  vpord .LCPI1_3(%rip){1to16}, %zmm1, %zmm1
  vpcmpltub .LCPI1_2(%rip), %zmm0, %k1
  vmovdqu8 %zmm1, %zmm0 {%k1}
  retq

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

1. Check that no other contributor is working on this issue. If someone is assigned to the issue or claimed to be working on it, ping the person. After one week without a response, the assignee may be changed.
2. Leave a comment indicating that you are working on the issue, or just create a pull request after following the steps below. Mention this issue in the description of the pull request.
3. Fix the issue locally.
4. Run the test suite locally. Remember that the subdirectories under test/ create fine-grained testing targets, so you can e.g. use make check-clang-ast to only run Clang's AST tests.
5. Create a Git commit.
6. Run git clang-format HEAD~1 to format your changes.
7. Open a pull request to the upstream repository on GitHub. Detailed instructions can be found in GitHub's documentation. Mention this issue in the description of the pull request.

If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

https://gcc.godbolt.org/z/63scvzTGT ```ll define <64 x i8> @select_add(<64 x i8> %0, <64 x i8> %1) { %add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65> %add1 = add <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32> %icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26> %res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0 ret <64 x i8> %res }

define <64 x i8> @select_or(<64 x i8> %0, <64 x i8> %1) {
%add0 = add <64 x i8> %0, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65>
%add1 = or disjoint <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
%icmp = icmp ult <64 x i8> %add0, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26>
%res = select <64 x i1> %icmp, <64 x i8> %add1, <64 x i8> %add0
ret <64 x i8> %res
}

While the select_add case correctly folds an add into a predicated instruction:
```s
select_add: # @<!-- -->select_add
  vpaddb .LCPI0_0(%rip), %zmm0, %zmm0
  vpcmpltub .LCPI0_1(%rip), %zmm0, %k1
  vpaddb .LCPI0_2(%rip), %zmm1, %zmm0 {%k1}
  retq

Using an add-like or-disjoint node fails to folds into the same add predicated instruction:

select_or: # @<!-- -->select_or
  vpaddb .LCPI1_0(%rip), %zmm0, %zmm0
  vpord .LCPI1_3(%rip){1to16}, %zmm1, %zmm1
  vpcmpltub .LCPI1_2(%rip), %zmm0, %k1
  vmovdqu8 %zmm1, %zmm0 {%k1}
  retq

[xyz-harshal]

I would like to work on this issue!

[xyz-harshal]

Why select_add Folds Correctly

• The vpaddb instruction performs packed byte addition, adding a constant vector of -65 to all 64 bytes in the zmm0 register in parallel.
• Since vpaddb operates at byte granularity, it processes 64 × 8-bit elements simultaneously with independent arithmetic on each byte.
• The vpcmpltub instruction generates a 64-bit mask register k1, where each bit corresponds to one 8-bit element in zmm0. Each mask bit controls whether the corresponding byte will be updated or preserved during predicated execution.
• During instruction selection, the LLVM backend successfully folds the select and second add operations into a single predicated vpaddb instruction with merge-masking ({%k1}). This is possible because the mask granularity (64 bits for 64 bytes) matches the instruction's native element size (8-bit bytes), eliminating any granularity mismatch.

Why select_or Fails to Fold Correctly

• Unlike arithmetic instructions, AVX-512 lacks byte-granularity predicated logical operations. The vpord instruction (Vector Packed OR Doubleword) operates on 32-bit elements, processing the 512-bit register as 16 × 32-bit doublewords rather than 64 × 8-bit bytes.
• The vpcmpltub comparison produces a 64-bit mask k1 with byte-level granularity (1 bit per 8-bit element).
• A fundamental element granularity mismatch prevents instruction folding: the predicated vpord would interpret the mask register at 32-bit granularity (using only 16 bits of k1), where each mask bit controls a 32-bit chunk (4 bytes). This coarse-grained masking cannot represent the fine-grained byte-level selection required by the original IR semantics.
• With this granularity mismatch, 48 bits of the k1 mask would be ignored, losing the byte-level selection control needed for correctness.
• To maintain semantic correctness, the LLVM backend must execute the vpord unconditionally on all elements, then use a separate vmovdqu8 instruction with byte-level merge-masking ({%k1}) to perform the conditional selection at the correct 8-bit granularity.
• This results in a 4-instruction sequence instead of the optimal 3-instruction sequence, representing a missed optimization opportunity due to ISA limitations.

Potential Solutions

1. ISA Extension (Hardware): Add byte-granularity predicated logical instructions (vporb, vpandb, vpxorb) to AVX-512_BW. This requires CPU microarchitecture changes and is beyond the scope of compiler optimization.

2. Pattern Matching Improvement (Software): Enhance the LLVM X86 backend to recognize that or disjoint with disjoint operands is semantically equivalent to add and can be lowered to vpaddb when byte-level predication is required. Since the disjoint flag guarantees (a | b) == (a + b) for the given operands, this transformation is semantically correct and would enable the same instruction folding optimization.

The most practical solution is option 2: teaching the backend's instruction selector to lower or disjoint as add when targeting predicated byte operations, exploiting the semantic equivalence guaranteed by the disjoint attribute.

[RKSimon]

Yes, for the AVX512BW VPADD patterns we need to be able to match addlike instead of just add opnodes in the avx512_binop_rm_vl_all expansion - aarch64 uses something similar add_and_or_is_add which we can hopefully convert to a generic addlike form that can be reused.

[xyz-harshal]

Alright,

llvm-project/llvm/lib/Target/X86/X86InstrAVX512.td

defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
                                    SchedWriteVecALU, 1>;

This line says that when you see an add operation in the SelectionDAG, it matches it to the VPADDB instruction.
It's currently static, but what we want is to match any add-like operation in SelectionDAG to the VPADDB instruction.
AArch64 already has an add_and_or_is_add function which basically checks if the opcode is add and returns true, or else checks if an OR node has the disjoint flag set or if the operands provably don't overlap.
What we can do is implement the same in X86 code:

llvm-project/llvm/include/llvm/GlobalISel/TargetSelectionDAG.td

def addlike : PatFrags<(ops node:$lhs, node:$rhs),
                         [(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
   if (Op.getOpcode() == ISD::ADD)
     return true;
   return CurDAG->isADDLike(Op);
}]> {
  let GISelPredicateCode = [{
     return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));
  }];
}

The addlike function is generic so all targets can use it, and it has the same logic as the AArch64 version.
Finally, replace add with addlike:

defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", addlike,
                                    SchedWriteVecALU, 1>;

Will this solve the issue?
number of files changed = 2

[RKSimon]

Not sure if addlike will work directly - you might have to refactor avx512_binop_rm_vl_all

[xyz-harshal]

@RKSimon
llvm-project/llvm/lib/Target/X86/X86InstrAVX512.td

defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
                                    SchedWriteVecALU, 1>;

In the above code add is of type SDNode, that is it will not accept addlike which is of datatype PatFrags.

multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
                                  bits<8> opc_d, bits<8> opc_q,
                                  string OpcodeStr, SDNode OpNode,
                                  X86SchedWriteWidths sched,
                                  bit IsCommutable = 0> {
  defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
                                    sched, HasAVX512, IsCommutable>,
              avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
                                    sched, HasBWI, IsCommutable>;
}

Above can we make avx512_binop_rm_vl_all to accept OpNode of both SDNode and PatFrags datatype?

[RKSimon]

Sorry for the delay - maybe take a look at AVX512_maskable_cmp - which casts both SDNode and PatFrag to a common dag arg class?