C.SRLI RISCV instruction doesn't enforce its shamt to be less than 32 #164186
Description
The RISCV ISA manual (page 116) says C.SRLI shift amount must always be non-0, and under the 32-bit arch must be less than 32 (equivaliently, that shamt[5] must be 0). The reason being that shamt[5] == 1 under the 32-bit arch is a custom subspace for third party instructions.
This doesn't appear to be the case with LLVM RISCV target:
Possible Solutions
I first thought of unconditionally setting shamt[5] (Instruction[12]) to 0, but the spec's wording allows the bit to be non-zero in case of the 64-bit arch, and indeed the SAIL description of the RISCV architecture allows the shift amount to exceed 32 if the architecture is 64 bit.