[CodeGen] Add MachineRegisterClassInfo analysis pass #164877
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Which is a wrapper of `RegisterClassInfo`. This can cache the result of `RegisterClassInfo` and hence we can reduce compile time.
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@llvm/pr-subscribers-backend-arm @llvm/pr-subscribers-backend-powerpc Author: Patrick Simmons (linuxrocks123) ChangesThis is an updated version of PR #120690 Patch is 58.68 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/164877.diff 25 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index c90ff4f3daa47..298ce32702d41 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -74,7 +74,7 @@ class MachinePipeliner : public MachineFunctionPass {
const MachineDominatorTree *MDT = nullptr;
const InstrItineraryData *InstrItins = nullptr;
const TargetInstrInfo *TII = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
bool disabledByPragma = false;
unsigned II_setByPragma = 0;
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 5a2aee2fa7643..0ee68c35baa19 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -147,13 +147,7 @@ struct LLVM_ABI MachineSchedContext {
const TargetMachine *TM = nullptr;
AAResults *AA = nullptr;
LiveIntervals *LIS = nullptr;
-
RegisterClassInfo *RegClassInfo;
-
- MachineSchedContext();
- MachineSchedContext &operator=(const MachineSchedContext &other) = delete;
- MachineSchedContext(const MachineSchedContext &other) = delete;
- virtual ~MachineSchedContext();
};
/// MachineSchedRegistry provides a selection of available machine instruction
diff --git a/llvm/include/llvm/CodeGen/RegisterClassInfo.h b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
index 078ae80915fed..3ea6ab619d1ca 100644
--- a/llvm/include/llvm/CodeGen/RegisterClassInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
@@ -19,6 +19,8 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegister.h"
#include "llvm/Support/Compiler.h"
@@ -27,6 +29,8 @@
namespace llvm {
+class MachineRegisterClassAnalysis;
+
class RegisterClassInfo {
struct RCInfo {
unsigned Tag = 0;
@@ -94,6 +98,14 @@ class RegisterClassInfo {
LLVM_ABI void runOnMachineFunction(const MachineFunction &MF,
bool Rev = false);
+ bool invalidate(MachineFunction &, const PreservedAnalyses &PA,
+ MachineFunctionAnalysisManager::Invalidator &) {
+ // Check whether the analysis has been explicitly invalidated. Otherwise,
+ // it's stateless and remains preserved.
+ auto PAC = PA.getChecker<MachineRegisterClassAnalysis>();
+ return !PAC.preservedWhenStateless();
+ }
+
/// getNumAllocatableRegs - Returns the number of actually allocatable
/// registers in RC in the current function.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
@@ -158,6 +170,39 @@ class RegisterClassInfo {
LLVM_ABI unsigned computePSetLimit(unsigned Idx) const;
};
+class MachineRegisterClassAnalysis
+ : public AnalysisInfoMixin<MachineRegisterClassAnalysis> {
+ friend AnalysisInfoMixin<MachineRegisterClassAnalysis>;
+
+ static AnalysisKey Key;
+
+public:
+ using Result = RegisterClassInfo;
+
+ Result run(MachineFunction &, MachineFunctionAnalysisManager &);
+};
+
+class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass {
+ virtual void anchor();
+
+ RegisterClassInfo RCI;
+
+public:
+ static char ID;
+
+ MachineRegisterClassInfoWrapperPass();
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesAll();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ RegisterClassInfo &getRCI() { return RCI; }
+ const RegisterClassInfo &getRCI() const { return RCI; }
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index cd774e7888e64..68f3d41e170cb 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -218,6 +218,7 @@ LLVM_ABI void initializeStaticDataAnnotatorPass(PassRegistry &);
LLVM_ABI void initializeMachinePipelinerPass(PassRegistry &);
LLVM_ABI void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeMachineRegionInfoPassPass(PassRegistry &);
+LLVM_ABI void initializeMachineRegisterClassInfoWrapperPassPass(PassRegistry &);
LLVM_ABI void
initializeMachineSanitizerBinaryMetadataLegacyPass(PassRegistry &);
LLVM_ABI void initializeMIR2VecVocabLegacyAnalysisPass(PassRegistry &);
@@ -343,6 +344,7 @@ LLVM_ABI void initializeWindowsSecureHotPatchingPass(PassRegistry &);
LLVM_ABI void initializeWinEHPreparePass(PassRegistry &);
LLVM_ABI void initializeWriteBitcodePassPass(PassRegistry &);
LLVM_ABI void initializeXRayInstrumentationLegacyPass(PassRegistry &);
+>>>>>>> master
} // end namespace llvm
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 04a0da06fb6ec..d22a76b8e515b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -79,6 +79,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
MachineOptimizationRemarkEmitterAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
MachinePostDominatorTreeAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info",
+ MachineRegisterClassAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-uniformity", MachineUniformityAnalysis())
MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 1846880b0c181..e5e16b0ab645d 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -38,7 +38,7 @@ class BreakFalseDeps : public MachineFunctionPass {
MachineFunction *MF = nullptr;
const TargetInstrInfo *TII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
/// List of undefined register reads in this block in forward order.
std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
@@ -57,6 +57,7 @@ class BreakFalseDeps : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
AU.addRequired<ReachingDefInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -101,6 +102,7 @@ class BreakFalseDeps : public MachineFunctionPass {
char BreakFalseDeps::ID = 0;
INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
@@ -151,7 +153,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
// max clearance or clearance higher than Pref.
unsigned MaxClearance = 0;
unsigned MaxClearanceReg = OriginalReg;
- ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
+ ArrayRef<MCPhysReg> Order = RegClassInfo->getOrder(OpRC);
for (MCPhysReg Reg : Order) {
unsigned Clearance = RDI->getClearance(MI, Reg);
if (Clearance <= MaxClearance)
@@ -282,10 +284,9 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
TII = MF->getSubtarget().getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
RDI = &getAnalysis<ReachingDefInfoWrapperPass>().getRDI();
- RegClassInfo.runOnMachineFunction(mf, /*Rev=*/true);
-
LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");
// Skip Dead blocks due to ReachingDefAnalysis has no idea about instructions
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index 54e2a009b464d..37ef58aafefae 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -73,7 +73,7 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Ensemble *TraceEnsemble = nullptr;
MachineBlockFrequencyInfo *MBFI = nullptr;
ProfileSummaryInfo *PSI = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
TargetSchedModel TSchedModel;
@@ -130,6 +130,7 @@ char &llvm::MachineCombinerID = MachineCombiner::ID;
INITIALIZE_PASS_BEGIN(MachineCombiner, DEBUG_TYPE,
"Machine InstCombiner", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineTraceMetricsWrapperPass)
INITIALIZE_PASS_END(MachineCombiner, DEBUG_TYPE, "Machine InstCombiner",
false, false)
@@ -139,6 +140,8 @@ void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
+ AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
AU.addRequired<MachineTraceMetricsWrapperPass>();
AU.addPreserved<MachineTraceMetricsWrapperPass>();
AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
@@ -571,7 +574,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
bool OptForSize = llvm::shouldOptimizeForSize(MBB, PSI, MBFI);
bool DoRegPressureReduce =
- TII->shouldReduceRegisterPressure(MBB, &RegClassInfo);
+ TII->shouldReduceRegisterPressure(MBB, RegClassInfo);
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
@@ -730,7 +733,7 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
&getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
nullptr;
TraceEnsemble = nullptr;
- RegClassInfo.runOnMachineFunction(MF);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
if (!TII->useMachineCombiner()) {
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index a717d9e4a618d..9267c4effe614 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -238,6 +238,7 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
"Modulo Software Pipelining", false, false)
@@ -385,8 +386,8 @@ bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) {
MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
TII = MF->getSubtarget().getInstrInfo();
- RegClassInfo.runOnMachineFunction(*MF);
for (const auto &L : *MLI)
scheduleLoop(*L);
@@ -611,7 +612,7 @@ bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
SwingSchedulerDAG SMS(
- *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), RegClassInfo,
+ *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), *RegClassInfo,
II_setByPragma, LI.LoopPipelinerInfo.get(), AA);
MachineBasicBlock *MBB = L.getHeader();
@@ -642,6 +643,8 @@ void MachinePipeliner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
+ AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
AU.addRequired<TargetPassConfig>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -654,7 +657,8 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) {
Context.TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
Context.AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Context.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- Context.RegClassInfo->runOnMachineFunction(*MF);
+ Context.RegClassInfo =
+ &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
WindowScheduler WS(&Context, L);
return WS.run();
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3ed10454f76c5..0d9192b5daa08 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -302,14 +302,6 @@ void ScheduleDAGMutation::anchor() {}
// Machine Instruction Scheduling Pass and Registry
//===----------------------------------------------------------------------===//
-MachineSchedContext::MachineSchedContext() {
- RegClassInfo = new RegisterClassInfo();
-}
-
-MachineSchedContext::~MachineSchedContext() {
- delete RegClassInfo;
-}
-
namespace llvm {
namespace impl_detail {
@@ -332,6 +324,7 @@ class MachineSchedulerImpl : public MachineSchedulerBase {
MachineDominatorTree &MDT;
AAResults &AA;
LiveIntervals &LIS;
+ RegisterClassInfo &RegClassInfo;
};
MachineSchedulerImpl() {}
@@ -432,6 +425,8 @@ void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
+ AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -444,6 +439,7 @@ INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
@@ -555,6 +551,7 @@ bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
this->TM = &TM;
AA = &Analyses.AA;
LIS = &Analyses.LIS;
+ RegClassInfo = &Analyses.RegClassInfo;
if (VerifyScheduling) {
LLVM_DEBUG(LIS->dump());
@@ -564,7 +561,6 @@ bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
else
MF->verify(*MFAM, MSchedBanner, &errs());
}
- RegClassInfo->runOnMachineFunction(*MF);
// Instantiate the selected scheduler for this target, function, and
// optimization level.
@@ -660,8 +656,11 @@ bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ auto &RegClassInfo =
+ getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
+
Impl.setLegacyPass(this);
- return Impl.run(MF, TM, {MLI, MDT, AA, LIS});
+ return Impl.run(MF, TM, {MLI, MDT, AA, LIS, RegClassInfo});
}
MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM)
@@ -693,8 +692,9 @@ MachineSchedulerPass::run(MachineFunction &MF,
.getManager();
auto &AA = FAM.getResult<AAManager>(MF.getFunction());
auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ auto &RegClassInfo = MFAM.getResult<MachineRegisterClassAnalysis>(MF);
Impl->setMFAM(&MFAM);
- bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS});
+ bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS, RegClassInfo});
if (!Changed)
return PreservedAnalyses::all();
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index cdcb29d92bfe6..65d11a7df7d89 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -135,7 +135,7 @@ class MachineSinking {
MachineBlockFrequencyInfo *MBFI = nullptr;
const MachineBranchProbabilityInfo *MBPI = nullptr;
AliasAnalysis *AA = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
TargetSchedModel SchedModel;
// Required for split critical edge
LiveIntervals *LIS;
@@ -204,9 +204,10 @@ class MachineSinking {
MachineLoopInfo *MLI, SlotIndexes *SI, LiveIntervals *LIS,
MachineCycleInfo *CI, ProfileSummaryInfo *PSI,
MachineBlockFrequencyInfo *MBFI,
- const MachineBranchProbabilityInfo *MBPI, AliasAnalysis *AA)
+ const MachineBranchProbabilityInfo *MBPI, AliasAnalysis *AA,
+ RegisterClassInfo *RegClassInfo)
: DT(DT), PDT(PDT), CI(CI), PSI(PSI), MBFI(MBFI), MBPI(MBPI), AA(AA),
- LIS(LIS), SI(SI), LV(LV), MLI(MLI),
+ RegClassInfo(RegClassInfo), LIS(LIS), SI(SI), LV(LV), MLI(MLI),
EnableSinkAndFold(EnableSinkAndFold) {}
bool run(MachineFunction &MF);
@@ -306,8 +307,10 @@ class MachineSinkingLegacy : public MachineFunctionPass {
AU.addRequired<MachinePostDominatorTreeWrapperPass>();
AU.addRequired<MachineCycleInfoWrapperPass>();
AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
AU.addPreserved<MachineCycleInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
+ AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
if (UseBlockFreqInfo)
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
@@ -327,6 +330,7 @@ INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking",
false, false)
@@ -773,8 +777,9 @@ MachineSinkingPass::run(MachineFunction &MF,
auto *SI = MFAM.getCachedResult<SlotIndexesAnalysis>(MF);
auto *LV = MFAM.getCachedResult<LiveVariablesAnalysis>(MF);
auto *MLI = MFAM.getCachedResult<MachineLoopAnalysis>(MF);
+ auto *RegClassInfo = &MFAM.getResult<MachineRegisterClassAnalysis>(MF);
MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI,
- MBFI, MBPI, AA);
+ MBFI, MBPI, AA, RegClassInfo);
bool Changed = Impl.run(MF);
if (!Changed)
return PreservedAnalyses::all();
@@ -819,9 +824,11 @@ bool MachineSinkingLegacy::runOnMachineFunction(MachineFunction &MF) {
auto *LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
auto *MLIWrapper = getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
auto *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
+ auto *RegClassInfo =
+ &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI,
- MBFI, MBPI, AA);
+ MBFI, MBPI, AA, RegClassInfo);
return Impl.run(MF);
}
@@ -833,8 +840,6 @@ bool MachineSinking::run(MachineFunction &MF) {
TRI = STI->getRegisterInfo();
MRI = &MF.getRegInfo();
- RegClassInfo.runOnMachineFunction(MF);
-
bool EverMadeChange = false;
while (true) {
@@ -1202,7 +1207,7 @@ MachineSinking::getBBRegisterPressure(const MachineBasicBlock &MBB,
RegPressureTracker RPTracker(Pressure);
// Initialize the register pressure tracker.
- RPTracker.init(MBB.getParent(), &RegC...
[truncated]
|
🐧 Linux x64 Test Results
All tests passed but another part of the build failed. Click on a failure below to see the details. lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/ShrinkWrap.cpp.oIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
Contributor
|
For AMDGPU it still seems like we are running the analysis too many times. I would expect one initial run plus maybe another one after the wwm alloc pass. Most other passes should preserve this. |
arsenm
reviewed
Nov 21, 2025
| const InstrItineraryData *InstrItins = nullptr; | ||
| const TargetInstrInfo *TII = nullptr; | ||
| RegisterClassInfo RegClassInfo; | ||
| RegisterClassInfo *RegClassInfo = nullptr; |
Contributor
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Suggested change
| RegisterClassInfo *RegClassInfo = nullptr; | |
| const RegisterClassInfo *RegClassInfo = nullptr; |
| INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) | ||
| INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) | ||
| INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) | ||
| INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) |
Contributor
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Sort this alphabetically with the other pass dependencies
Comment on lines
+388
to
+389
| RegisterClassInfo *RegClassInfo = | ||
| &MFAM.getResult<MachineRegisterClassAnalysis>(MF); |
Contributor
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Suggested change
| RegisterClassInfo *RegClassInfo = | |
| &MFAM.getResult<MachineRegisterClassAnalysis>(MF); | |
| const RegisterClassInfo &RegClassInfo = | |
| MFAM.getResult<MachineRegisterClassAnalysis>(MF); |
| SlotIndexes *SI = nullptr; | ||
| const MachineLoopInfo *Loops = nullptr; | ||
| RegisterClassInfo RegClassInfo; | ||
| RegisterClassInfo *RegClassInfo = nullptr; |
Contributor
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Suggested change
| RegisterClassInfo *RegClassInfo = nullptr; | |
| const RegisterClassInfo *RegClassInfo = nullptr; |
| const TargetSubtargetInfo &STI = fn.getSubtarget(); | ||
| TRI = STI.getRegisterInfo(); | ||
| TII = STI.getInstrInfo(); | ||
|
|
| class ShrinkWrapImpl { | ||
| /// Hold callee-saved information. | ||
| RegisterClassInfo RCI; | ||
| RegisterClassInfo *RCI = nullptr; |
Contributor
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Suggested change
| RegisterClassInfo *RCI = nullptr; | |
| const RegisterClassInfo *RCI = nullptr; |
Contributor
Author
|
@jayfoad yes all I've been doing is keeping this up-to-date with master. I think the right way to do this is to force this analysis to be preserved except when explicitly invalidated by a pass, but I am not sure how to do that. If you or @arsenm happen to know what hook makes that happen off the top of your head, that may save me some research time. |
Contributor
This is how the new pass manager works, but not the old. For the old pass manager, it's probably easiest to just brute force add this as preserved to all of the passes. I'm not sure there's a simple way to invert this there |
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This is an updated version of PR #120690