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@AZero13 AZero13 commented Oct 25, 2025

This prevents overcorrection to the mask, especially if it is valid already.

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llvmbot commented Oct 25, 2025

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/165106.diff

1 Files Affected:

  • (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+1-1)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 313ae3d68fb83..9b7955eda8f8d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20178,7 +20178,7 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   // code won't do this, so we have to do it explicitly to avoid an infinite
   // loop in obscure cases.)
   if (ExpandedMask == ~0U)
-    return TLO.CombineTo(Op, Op.getOperand(0));
+    return false;
 
   auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
     return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;

@AZero13 AZero13 marked this pull request as draft October 25, 2025 16:28
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github-actions bot commented Oct 25, 2025

✅ With the latest revision this PR passed the C/C++ code formatter.

@AZero13 AZero13 changed the title Remove Manual combine-to [ARM] Only change mask if demanded bits says we can optimize Oct 25, 2025
@AZero13 AZero13 force-pushed the and-s branch 24 times, most recently from 4a57f0e to 56c708c Compare October 27, 2025 17:49
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AZero13 commented Oct 27, 2025

This is the best I can do without regressions @davemgreen

To remove the workarounds I have to improve the ubfx code which involves porting getUsefulBits from AArch64, which is a very large effort.

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AZero13 commented Oct 28, 2025

@rj-jesus Thoughts on this?

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AZero13 commented Nov 7, 2025

@arsenm Here.

This prevents overcorrection to the mask, especially if it is valid already.
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2 participants