[clang][X86] Allow VALIGND/Q element-shift intrinsics in constexpr evaluation #168206

0xzre · 2025-11-15T13:46:02Z

…allow VALIGND/Q element shift intrinsics to be used in constexpr

github-actions · 2025-11-15T13:46:21Z

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llvmbot · 2025-11-15T13:46:49Z

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-clang

Author: Muhammad Abdul (0xzre)

Changes

Fixes #167681

Full diff: https://github.com/llvm/llvm-project/pull/168206.diff

4 Files Affected:

(modified) clang/include/clang/Basic/BuiltinsX86.td (+5-5)
(modified) clang/lib/AST/ByteCode/InterpBuiltin.cpp (+21)
(modified) clang/lib/AST/ExprConstant.cpp (+24)
(added) clang/test/AST/ByteCode/x86-valign-builtins.cpp (+53)

diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index 69d18679fd6ec..aad0361ba9a8b 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -1072,24 +1072,24 @@ let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
   def storeaps512_mask : X86Builtin<"void(_Vector<16, float *>, _Vector<16, float>, unsigned short)">;
 }
 
-let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
+let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in {
   def alignq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int)">;
   def alignd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">;
 }
 
-let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
+let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in {
   def alignd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Constant int)">;
 }
 
-let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
+let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<256>] in {
   def alignd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Constant int)">;
 }
 
-let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
+let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in {
   def alignq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>, _Constant int)">;
 }
 
-let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
+let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<256>] in {
   def alignq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant int)">;
 }
 
diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
index cee3c1b8cf8f3..7c08475065d9d 100644
--- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
+++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
@@ -4774,6 +4774,27 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
           return std::pair<unsigned, int>{VecIdx, ElemIdx};
         });
 
+  case X86::BI__builtin_ia32_alignd128:
+  case X86::BI__builtin_ia32_alignd256:
+  case X86::BI__builtin_ia32_alignd512:
+  case X86::BI__builtin_ia32_alignq128:
+  case X86::BI__builtin_ia32_alignq256:
+  case X86::BI__builtin_ia32_alignq512: {
+    const unsigned NumElts =
+        Call->getType()->castAs<VectorType>()->getNumElements();
+    return interp__builtin_ia32_shuffle_generic(
+        S, OpPC, Call, [NumElts](unsigned DstIdx, unsigned Shift) {
+          unsigned Imm = Shift & 0xFF;
+          unsigned EffectiveShift = Imm & (NumElts - 1);
+          unsigned SourcePos = DstIdx + EffectiveShift;
+          unsigned VecIdx = SourcePos < NumElts ? 1u : 0u;
+          unsigned ElemIdx =
+              SourcePos < NumElts ? SourcePos : SourcePos - NumElts;
+          return std::pair<unsigned, int>{VecIdx,
+                                          static_cast<int>(ElemIdx)};
+        });
+  }
+
   default:
     S.FFDiag(S.Current->getLocation(OpPC),
              diag::note_invalid_subexpr_in_const_expr)
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 29357eec2eeb6..b3f17da8e1158 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -13551,6 +13551,30 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
       return false;
     return Success(R, E);
   }
+  case X86::BI__builtin_ia32_alignd128:
+  case X86::BI__builtin_ia32_alignd256:
+  case X86::BI__builtin_ia32_alignd512:
+  case X86::BI__builtin_ia32_alignq128:
+  case X86::BI__builtin_ia32_alignq256:
+  case X86::BI__builtin_ia32_alignq512: {
+    APValue R;
+    const unsigned NumElts =
+        E->getType()->castAs<VectorType>()->getNumElements();
+    if (!evalShuffleGeneric(
+            Info, E, R, [NumElts](unsigned DstIdx, unsigned Shift) {
+              unsigned Imm = Shift & 0xFF;
+              unsigned EffectiveShift = Imm & (NumElts - 1);
+              unsigned SourcePos = DstIdx + EffectiveShift;
+              unsigned VecIdx = SourcePos < NumElts ? 1 : 0;
+              unsigned ElemIdx =
+                  SourcePos < NumElts ? SourcePos : SourcePos - NumElts;
+
+              return std::pair<unsigned, int>{VecIdx,
+                                              static_cast<int>(ElemIdx)};
+            }))
+      return false;
+    return Success(R, E);
+  }
   case X86::BI__builtin_ia32_permvarsi256:
   case X86::BI__builtin_ia32_permvarsf256:
   case X86::BI__builtin_ia32_permvardf512:
diff --git a/clang/test/AST/ByteCode/x86-valign-builtins.cpp b/clang/test/AST/ByteCode/x86-valign-builtins.cpp
new file mode 100644
index 0000000000000..a54e72fab90ce
--- /dev/null
+++ b/clang/test/AST/ByteCode/x86-valign-builtins.cpp
@@ -0,0 +1,53 @@
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512dq -verify=expected -fexperimental-new-constant-interpreter %s
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512dq -verify=ref %s
+
+// expected-no-diagnostics
+// ref-no-diagnostics
+
+#define __MM_MALLOC_H
+#include <immintrin.h>
+
+using v4si = int __attribute__((vector_size(16)));
+using v8si = int __attribute__((vector_size(32)));
+using v16si = int __attribute__((vector_size(64)));
+using v4di = long long __attribute__((vector_size(32)));
+
+constexpr v4si test_alignr_epi32_128() {
+  v4si A = {100, 200, 300, 400};
+  v4si B = {10, 20, 30, 40};
+  return (v4si)_mm_alignr_epi32((__m128i)A, (__m128i)B, 1);
+}
+
+constexpr v8si test_alignr_epi32_256() {
+  v8si A = {100, 200, 300, 400, 500, 600, 700, 800};
+  v8si B = {1, 2, 3, 4, 5, 6, 7, 8};
+  return (v8si)_mm256_alignr_epi32((__m256i)A, (__m256i)B, 3);
+}
+
+constexpr v16si test_alignr_epi32_512_wrap() {
+  v16si A = {100, 200, 300, 400, 500, 600, 700, 800,
+             900, 1000, 1100, 1200, 1300, 1400, 1500, 1600};
+  v16si B = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  return (v16si)_mm512_alignr_epi32((__m512i)A, (__m512i)B, 19);
+}
+
+constexpr v4di test_alignr_epi64_256() {
+  v4di A = {10, 11, 12, 13};
+  v4di B = {1, 2, 3, 4};
+  return (v4di)_mm256_alignr_epi64((__m256i)A, (__m256i)B, 2);
+}
+
+constexpr v4si R128 = test_alignr_epi32_128();
+static_assert(R128[0] == 20 && R128[1] == 30 && R128[2] == 40 && R128[3] == 100);
+
+constexpr v8si R256 = test_alignr_epi32_256();
+static_assert(R256[0] == 4 && R256[1] == 5 && R256[2] == 6 && R256[3] == 7);
+static_assert(R256[4] == 8 && R256[5] == 100 && R256[6] == 200 && R256[7] == 300);
+
+constexpr v16si R512 = test_alignr_epi32_512_wrap();
+static_assert(R512[0] == 3 && R512[1] == 4 && R512[2] == 5 && R512[3] == 6);
+static_assert(R512[8] == 11 && R512[9] == 12 && R512[10] == 13 && R512[11] == 14);
+static_assert(R512[12] == 15 && R512[13] == 100 && R512[14] == 200 && R512[15] == 300);
+
+constexpr v4di R64 = test_alignr_epi64_256();
+static_assert(R64[0] == 3 && R64[1] == 4 && R64[2] == 10 && R64[3] == 11);

github-actions · 2025-11-15T15:44:46Z

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff origin/main HEAD --extensions cpp,c -- clang/lib/AST/ByteCode/InterpBuiltin.cpp clang/lib/AST/ExprConstant.cpp clang/test/CodeGen/X86/avx512f-builtins.c clang/test/CodeGen/X86/avx512vl-builtins.c --diff_from_common_commit

⚠️
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing origin/main to the base branch/commit you want to compare against.
⚠️

View the diff from clang-format here.

diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
index 1a8a2a357..3605942c3 100644
--- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
+++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
@@ -4781,8 +4781,7 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
   case X86::BI__builtin_ia32_alignq128:
   case X86::BI__builtin_ia32_alignq256:
   case X86::BI__builtin_ia32_alignq512: {
-    unsigned NumElems =
-        Call->getType()->castAs<VectorType>()->getNumElements();
+    unsigned NumElems = Call->getType()->castAs<VectorType>()->getNumElements();
     return interp__builtin_ia32_shuffle_generic(
         S, OpPC, Call, [NumElems](unsigned DstIdx, unsigned Shift) {
           unsigned Imm = Shift & 0xFF;

RKSimon

Tests should be added to the existing avx512*builtins.cpp files next to the corresponding intrinsics test coverage using the TEST_CONSTEXPR helpers - see #164078 for an example

clang/lib/AST/ByteCode/InterpBuiltin.cpp

0xzre · 2025-11-16T15:34:35Z

Tests should be added to the existing avx512*builtins.cpp files next to the corresponding intrinsics test coverage using the TEST_CONSTEXPR helpers - see #164078 for an example

Implemented the tests 👍

RKSimon · 2025-11-17T13:43:53Z

clang/lib/AST/ByteCode/InterpBuiltin.cpp

+          unsigned SourcePos = DstIdx + EffectiveShift;
+          unsigned VecIdx = SourcePos < NumElems ? 1u : 0u;
+          unsigned ElemIdx =
+              SourcePos < NumElems ? SourcePos : SourcePos - NumElems;


Suggested change

SourcePos < NumElems ? SourcePos : SourcePos - NumElems;

unsigned ElemIdx = SourcePos & (NumElems - 1);

oh nice, fixed

RKSimon · 2025-11-17T13:44:17Z

clang/lib/AST/ExprConstant.cpp

+              unsigned SourcePos = DstIdx + EffectiveShift;
+              unsigned VecIdx = SourcePos < NumElts ? 1 : 0;
+              unsigned ElemIdx =
+                  SourcePos < NumElts ? SourcePos : SourcePos - NumElts;


Suggested change

SourcePos < NumElts ? SourcePos : SourcePos - NumElts;

unsigned ElemIdx = SourcePos & (NumElems - 1);

[clang][X86] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - …

5e69309

…allow VALIGND/Q element shift intrinsics to be used in constexpr

llvmbot added clang Clang issues not falling into any other category backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:bytecode Issues for the clang bytecode constexpr interpreter labels Nov 15, 2025

RKSimon self-requested a review November 15, 2025 15:42

RKSimon requested changes Nov 15, 2025

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tbaederr reviewed Nov 15, 2025

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clang/lib/AST/ByteCode/InterpBuiltin.cpp Outdated Show resolved Hide resolved

0xzre added 3 commits November 16, 2025 15:48

fix vars & clang format

3fe153e

add test using TEST_CONSTEXPR on avx512*builtins.cpp

d17b6de

remove uneeded bytecode test

85ad38f

RKSimon self-requested a review November 17, 2025 12:54

RKSimon requested changes Nov 17, 2025

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high perf circular queues & fix format

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[clang][X86] Allow VALIGND/Q element-shift intrinsics in constexpr evaluation #168206

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	SourcePos < NumElems ? SourcePos : SourcePos - NumElems;
	unsigned ElemIdx = SourcePos & (NumElems - 1);

	SourcePos < NumElts ? SourcePos : SourcePos - NumElts;
	unsigned ElemIdx = SourcePos & (NumElems - 1);

[clang][X86] Allow VALIGND/Q element-shift intrinsics in constexpr evaluation #168206

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[clang][X86] Allow VALIGND/Q element-shift intrinsics in constexpr evaluation #168206

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