[RISC-V] Zilsd Improvements

[lenary]

I thought it might be good to centralise the TODO list for Zilsd support, so we can collaborate across orgs a little better.

Here are some possible improvements relating to Zilsd:

• Spills/Reloads ([RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled #153595)
• Callee-Saves?
• Allocation Priority of GPRPairs?

Craig remarked there's an interaction of Zilsd with Zfinx/Zdinx which we may need to resolve/improve. I don't have the details fully in my head.

NXP's tree with Zilsd support is here: https://github.com/nxp-auto-tools/llvm-project/tree/Zilsd/release/18.1.6 - but much of these changes have been reimplemented from scratch upstream already.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

I thought it might be good to centralise the TODO list for Zilsd support, so we can collaborate across orgs a little better.

Here are some possible improvements relating to Zilsd:

• Spills/Reloads ([RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled #153595)
• Callee-Saves?
• Allocation Priority of GPRPairs?

Craig remarked there's an interaction of Zilsd with Zfinx/Zdinx which we may need to resolve/improve. I don't have the details fully in my head.

NXP's tree with Zilsd support is here: https://github.com/nxp-auto-tools/llvm-project/tree/Zilsd/release/18.1.6 - but much of these changes have been reimplemented from scratch upstream already.

[topperc]

Zfinx uses LW_INX and SW_INX instructions that use GPRF32 regclass instead of GPR. These will not be picked up the by new pass. All Zfinx instructions use GPRF32 regclass. This was done to avoid 64-bit spills on RV64.

Naively, we would need to add PseudoLD_INX_OP/PseudoSD_INX_OPT and LD_INX_RV32/SD_INX_RV32 instructions and a GPRF32Pair register class.

I'm not sure we want to add the GPRF32Pair regclass, our register hierarchy is complicated enough already.

We could split the Zfinx instructions between RV32 and RV64 and use GPR for RV32. We already split for Zdinx to use GPRPair for RV32 and GPR for RV64. This requires duplicating a couple dozen instructions.

We could try using INSERT_SUBREG/EXTRACT_SUBREG around the load/stores to remove LW_INX/SW_INX. We could need to see how that affects what register class gets used for spills.

[lenary]

#169067 (comment) has some numbers about Zilsd ISel, for future reference.