AMDGPU/GlobalISel: Report RegBankLegalize errors using reportGISelFailure #169918
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Collaborator
Author
This stack of pull requests is managed by Graphite. Learn more about stacking. |
petar-avramovic
requested review from
Flakebi,
aemerson,
arsenm,
dstutt,
mbrkusanin and
piotrAMD
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Petar Avramovic (petar-avramovic) ChangesUse standard GlobalISel error reporting with reportGISelFailure Full diff: https://github.com/llvm/llvm-project/pull/169918.diff 5 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index 396d64625fb5c..839120da89711 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -435,7 +435,8 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
unsigned Opc = MI->getOpcode();
// Insert point for use operands needs some calculation.
if (Opc == AMDGPU::G_PHI) {
- RBLHelper.applyMappingPHI(*MI);
+ if (!RBLHelper.applyMappingPHI(*MI))
+ return false;
continue;
}
@@ -466,7 +467,8 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// S1 rules are in RegBankLegalizeRules.
}
- RBLHelper.findRuleAndApplyMapping(*MI);
+ if (!RBLHelper.findRuleAndApplyMapping(*MI))
+ return false;
}
// Sgpr S1 clean up combines:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 123fc5bf37a19..8ce18afcc326a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -32,28 +32,45 @@ using namespace AMDGPU;
RegBankLegalizeHelper::RegBankLegalizeHelper(
MachineIRBuilder &B, const MachineUniformityInfo &MUI,
const RegisterBankInfo &RBI, const RegBankLegalizeRules &RBLRules)
- : ST(B.getMF().getSubtarget<GCNSubtarget>()), B(B), MRI(*B.getMRI()),
- MUI(MUI), RBI(RBI), RBLRules(RBLRules), IsWave32(ST.isWave32()),
+ : MF(B.getMF()), ST(MF.getSubtarget<GCNSubtarget>()), B(B),
+ MRI(*B.getMRI()), MUI(MUI), RBI(RBI), MORE(MF, nullptr),
+ RBLRules(RBLRules), IsWave32(ST.isWave32()),
SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}
-void RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
- const SetOfRulesForOpcode &RuleSet = RBLRules.getRulesForOpc(MI);
- const RegBankLLTMapping &Mapping = RuleSet.findMappingForMI(MI, MRI, MUI);
+bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
+ const SetOfRulesForOpcode *RuleSet = RBLRules.getRulesForOpc(MI);
+ if (!RuleSet) {
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "No AMDGPU RegBankLegalize rules defined for opcode",
+ MI);
+ return false;
+ }
+
+ const RegBankLLTMapping *Mapping = RuleSet->findMappingForMI(MI, MRI, MUI);
+ if (!Mapping) {
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: none of the rules defined with "
+ "'Any' for MI's opcode matched MI",
+ MI);
+ return false;
+ }
SmallSet<Register, 4> WaterfallSgprs;
unsigned OpIdx = 0;
- if (Mapping.DstOpMapping.size() > 0) {
+ if (Mapping->DstOpMapping.size() > 0) {
B.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
- applyMappingDst(MI, OpIdx, Mapping.DstOpMapping);
+ if (!applyMappingDst(MI, OpIdx, Mapping->DstOpMapping))
+ return false;
}
- if (Mapping.SrcOpMapping.size() > 0) {
+ if (Mapping->SrcOpMapping.size() > 0) {
B.setInstr(MI);
- applyMappingSrc(MI, OpIdx, Mapping.SrcOpMapping, WaterfallSgprs);
+ applyMappingSrc(MI, OpIdx, Mapping->SrcOpMapping, WaterfallSgprs);
}
- lower(MI, Mapping, WaterfallSgprs);
+ lower(MI, *Mapping, WaterfallSgprs);
+ return true;
}
bool RegBankLegalizeHelper::executeInWaterfallLoop(
@@ -1055,7 +1072,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
}
}
-void RegBankLegalizeHelper::applyMappingDst(
+bool RegBankLegalizeHelper::applyMappingDst(
MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs) {
// Defs start from operand 0
@@ -1180,13 +1197,17 @@ void RegBankLegalizeHelper::applyMappingDst(
break;
}
case InvalidMapping: {
- LLVM_DEBUG(dbgs() << "Instruction with Invalid mapping: "; MI.dump(););
- llvm_unreachable("missing fast rule for MI");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: missing fast rule ('Div' or 'Uni') for", MI);
+ return false;
}
default:
llvm_unreachable("ID not supported");
}
}
+
+ return true;
}
void RegBankLegalizeHelper::applyMappingSrc(
@@ -1348,7 +1369,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
}
}
-void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
+bool RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
@@ -1371,16 +1392,17 @@ void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
MI.getOperand(i).setReg(NewUse.getReg(0));
}
- return;
+ return true;
}
- // ALL divergent i1 phis should be already lowered and inst-selected into PHI
- // with sgpr reg class and S1 LLT.
+ // ALL divergent i1 phis should have been lowered and inst-selected into PHI
+ // with sgpr reg class and S1 LLT in AMDGPUGlobalISelDivergenceLowering pass.
// Note: this includes divergent phis that don't require lowering.
if (Ty == LLT::scalar(1) && MUI.isDivergent(Dst)) {
- LLVM_DEBUG(dbgs() << "Divergent S1 G_PHI: "; MI.dump(););
- llvm_unreachable("Make sure to run AMDGPUGlobalISelDivergenceLowering "
- "before RegBankLegalize to lower lane mask(vcc) phis");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: Can't lower divergent S1 G_PHI",
+ MI);
+ return false;
}
// We accept all types that can fit in some register class.
@@ -1388,11 +1410,13 @@ void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
// Divergent G_PHIs have vgpr dst but inputs can be sgpr or vgpr.
if (Ty == LLT::scalar(32) || Ty == LLT::pointer(1, 64) ||
Ty == LLT::pointer(4, 64)) {
- return;
+ return true;
}
- LLVM_DEBUG(dbgs() << "G_PHI not handled: "; MI.dump(););
- llvm_unreachable("type not supported");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: type not supported for G_PHI",
+ MI);
+ return false;
}
[[maybe_unused]] static bool verifyRegBankOnOperands(MachineInstr &MI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
index 4f1c3c02fa5d6..254462c79fbd5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -12,6 +12,7 @@
#include "AMDGPURegBankLegalizeRules.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
namespace llvm {
@@ -27,11 +28,13 @@ namespace AMDGPU {
// to replace instruction. In other case InstApplyMethod will create new
// instruction(s).
class RegBankLegalizeHelper {
+ MachineFunction &MF;
const GCNSubtarget &ST;
MachineIRBuilder &B;
MachineRegisterInfo &MRI;
const MachineUniformityInfo &MUI;
const RegisterBankInfo &RBI;
+ MachineOptimizationRemarkEmitter MORE;
const RegBankLegalizeRules &RBLRules;
const bool IsWave32;
const RegisterBank *SgprRB;
@@ -81,10 +84,10 @@ class RegBankLegalizeHelper {
const RegisterBankInfo &RBI,
const RegBankLegalizeRules &RBLRules);
- void findRuleAndApplyMapping(MachineInstr &MI);
+ bool findRuleAndApplyMapping(MachineInstr &MI);
// Manual apply helpers.
- void applyMappingPHI(MachineInstr &MI);
+ bool applyMappingPHI(MachineInstr &MI);
void applyMappingTrivial(MachineInstr &MI);
private:
@@ -97,7 +100,7 @@ class RegBankLegalizeHelper {
const RegisterBank *getRegBankFromID(RegBankLLTMappingApplyID ID);
- void
+ bool
applyMappingDst(MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 6ec51e1be8aca..d07e356100508 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -243,7 +243,7 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
return _;
}
-const RegBankLLTMapping &
+const RegBankLLTMapping *
SetOfRulesForOpcode::findMappingForMI(const MachineInstr &MI,
const MachineRegisterInfo &MRI,
const MachineUniformityInfo &MUI) const {
@@ -260,17 +260,16 @@ SetOfRulesForOpcode::findMappingForMI(const MachineInstr &MI,
Slot = getFastPredicateSlot(LLTToId(MRI.getType(Reg)));
if (Slot != -1)
- return MUI.isUniform(Reg) ? Uni[Slot] : Div[Slot];
+ return MUI.isUniform(Reg) ? &Uni[Slot] : &Div[Slot];
}
// Slow search for more complex rules.
for (const RegBankLegalizeRule &Rule : Rules) {
if (Rule.Predicate.match(MI, MUI, MRI))
- return Rule.OperandMapping;
+ return &Rule.OperandMapping;
}
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("None of the rules defined for MI's opcode matched MI");
+ return nullptr;
}
void SetOfRulesForOpcode::addRule(RegBankLegalizeRule Rule) {
@@ -353,7 +352,7 @@ RegBankLegalizeRules::addRulesForIOpcs(std::initializer_list<unsigned> OpcList,
return RuleSetInitializer(OpcList, IRulesAlias, IRules, FastTypes);
}
-const SetOfRulesForOpcode &
+const SetOfRulesForOpcode *
RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
if (Opc == AMDGPU::G_INTRINSIC || Opc == AMDGPU::G_INTRINSIC_CONVERGENT ||
@@ -361,19 +360,15 @@ RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
Opc == AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
unsigned IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
auto IRAIt = IRulesAlias.find(IntrID);
- if (IRAIt == IRulesAlias.end()) {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("No rules defined for intrinsic opcode");
- }
- return IRules.at(IRAIt->second);
+ if (IRAIt == IRulesAlias.end())
+ return nullptr;
+ return &IRules.at(IRAIt->second);
}
auto GRAIt = GRulesAlias.find(Opc);
- if (GRAIt == GRulesAlias.end()) {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("No rules defined for generic opcode");
- }
- return GRules.at(GRAIt->second);
+ if (GRAIt == GRulesAlias.end())
+ return nullptr;
+ return &GRules.at(GRAIt->second);
}
// Syntactic sugar wrapper for predicate lambda that enables '&&', '||' and '!'.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 7e4ce7b43dc3b..1ac117304b76f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -287,7 +287,7 @@ class SetOfRulesForOpcode {
SetOfRulesForOpcode();
SetOfRulesForOpcode(FastRulesTypes FastTypes);
- const RegBankLLTMapping &
+ const RegBankLLTMapping *
findMappingForMI(const MachineInstr &MI, const MachineRegisterInfo &MRI,
const MachineUniformityInfo &MUI) const;
@@ -385,7 +385,7 @@ class RegBankLegalizeRules {
MRI = &_MRI;
};
- const SetOfRulesForOpcode &getRulesForOpc(MachineInstr &MI) const;
+ const SetOfRulesForOpcode *getRulesForOpc(MachineInstr &MI) const;
};
} // end namespace AMDGPU
|
petar-avramovic
force-pushed
the
users/petar-avramovic/stop-using-TPC
branch
from
f7d7bd9 to
a291032
Compare
petar-avramovic
force-pushed
the
users/petar-avramovic/graceful-crash-NoTPC
branch
from
a248fe0 to
3cddbc4
Compare
petar-avramovic
force-pushed
the
users/petar-avramovic/stop-using-TPC
branch
from
a291032 to
9c641ba
Compare
petar-avramovic
force-pushed
the
users/petar-avramovic/graceful-crash-NoTPC
branch
2 times, most recently
from
6d5beb9 to
e5be5bf
Compare
petar-avramovic
force-pushed
the
users/petar-avramovic/stop-using-TPC
branch
from
9c641ba to
120927c
Compare
petar-avramovic
force-pushed
the
users/petar-avramovic/graceful-crash-NoTPC
branch
from
e5be5bf to
1485d0e
Compare
…lure Use standard GlobalISel error reporting with reportGISelFailure and pass returning false instead of llvm_unreachable. Also enables -global-isel-abort=0 or 2 for -global-isel -new-reg-bank-select. Note: new-reg-bank-select with abort 0 or 2 runs LCSSA, while "intended use" without abort or with abort 1 does not run LCSSA.
petar-avramovic
force-pushed
the
users/petar-avramovic/graceful-crash-NoTPC
branch
from
1485d0e to
d202056
Compare
Collaborator
Author
|
more bool returns and proper error reports |
arsenm
approved these changes
Dec 2, 2025
Collaborator
Author
Merge activity
|
petar-avramovic
deleted the
users/petar-avramovic/graceful-crash-NoTPC
branch
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/116/builds/21693 Here is the relevant piece of the build log for the reference |
kcloudy0717
pushed a commit
to kcloudy0717/llvm-project
that referenced
this pull request
Dec 4, 2025
…lure (llvm#169918) Use standard GlobalISel error reporting with reportGISelFailure and pass returning false instead of llvm_unreachable. Also enables -global-isel-abort=0 or 2 for -global-isel -new-reg-bank-select. Note: new-reg-bank-select with abort 0 or 2 runs LCSSA, while "intended use" without abort or with abort 1 does not run LCSSA.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Use standard GlobalISel error reporting with reportGISelFailure
and pass returning false instead of llvm_unreachable.
Also enables -global-isel-abort=0 or 2 for -global-isel -new-reg-bank-select.
Note: new-reg-bank-select with abort 0 or 2 runs LCSSA,
while "intended use" without abort or with abort 1 does not run LCSSA.