shufflevector of load does not reduce load size

[arsenm]

Bugzilla Link	42424
Version	trunk
OS	All
CC	@RKSimon,@rotateright

Extended Description

define <4 x half> @​shuffle_v4f16_0101(<4 x half> addrspace(1)* nocapture readonly %arg0, <4 x half> addrspace(1)* nocapture readnone %arg1) {
%val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0, align 8
%shuffle = shufflevector <4 x half> %val0, <4 x half> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x half> %shuffle
}

I would expect instcombine to recognize that only the low half of the load is used, and reduce this to a load <2 x half>

[rotateright]

I was looking for what is effectively the inverse transform as part of bug 16739 and bug 21780 - a full/legal vector load would result in smaller IR and better codegen.

I'm not sure that we can do either of these transforms target-independently. At the least, we likely have to ask the data layout if the types are legal.

We do have load narrowing in SDAG already, so that might be a better place to implement this.