Skip to content

[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue #109439

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Sep 30, 2024
Merged

[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue #109439

Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c8fbbe4
[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue
jayfoad Sep 20, 2024
7796e26
Remove irrelevant FIXME
jayfoad Sep 30, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8884,8 +8884,9 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
// FIXME: Copies inserted in the block prolog for live-range split should also
Copy link
Collaborator

@cdevadas cdevadas Sep 23, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This FIXME isn't relevant anymore. We are including only the SGPR spills to the prolog.

Copy link
Contributor Author

@jayfoad jayfoad Sep 30, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Removed.

// be included.
return IsNullOrVectorRegister &&
(isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
(isSGPRSpill(Opcode) ||
(!MI.isTerminator() && Opcode != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
}

MachineInstrBuilder
Expand Down