diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index 52221762fed5d..45750f34fa200 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -20,6 +20,7 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TileShapeInfo.h"
+#include "llvm/IR/PassManager.h"
 #include "llvm/Pass.h"
 #include <cassert>
 
@@ -30,171 +31,210 @@ class MachineRegisterInfo;
 class raw_ostream;
 class TargetInstrInfo;
 
-  class VirtRegMap : public MachineFunctionPass {
-    MachineRegisterInfo *MRI = nullptr;
-    const TargetInstrInfo *TII = nullptr;
-    const TargetRegisterInfo *TRI = nullptr;
-    MachineFunction *MF = nullptr;
-
-    /// Virt2PhysMap - This is a virtual to physical register
-    /// mapping. Each virtual register is required to have an entry in
-    /// it; even spilled virtual registers (the register mapped to a
-    /// spilled register is the temporary used to load it from the
-    /// stack).
-    IndexedMap<MCRegister, VirtReg2IndexFunctor> Virt2PhysMap;
+class VirtRegMap {
+  MachineRegisterInfo *MRI = nullptr;
+  const TargetInstrInfo *TII = nullptr;
+  const TargetRegisterInfo *TRI = nullptr;
+  MachineFunction *MF = nullptr;
+
+  /// Virt2PhysMap - This is a virtual to physical register
+  /// mapping. Each virtual register is required to have an entry in
+  /// it; even spilled virtual registers (the register mapped to a
+  /// spilled register is the temporary used to load it from the
+  /// stack).
+  IndexedMap<MCRegister, VirtReg2IndexFunctor> Virt2PhysMap;
+
+  /// Virt2StackSlotMap - This is virtual register to stack slot
+  /// mapping. Each spilled virtual register has an entry in it
+  /// which corresponds to the stack slot this register is spilled
+  /// at.
+  IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
+
+  /// Virt2SplitMap - This is virtual register to splitted virtual register
+  /// mapping.
+  IndexedMap<Register, VirtReg2IndexFunctor> Virt2SplitMap;
+
+  /// Virt2ShapeMap - For X86 AMX register whose register is bound shape
+  /// information.
+  DenseMap<Register, ShapeT> Virt2ShapeMap;
+
+  /// createSpillSlot - Allocate a spill slot for RC from MFI.
+  unsigned createSpillSlot(const TargetRegisterClass *RC);
+
+public:
+  static constexpr int NO_STACK_SLOT = INT_MAX;
+
+  VirtRegMap() : Virt2StackSlotMap(NO_STACK_SLOT) {}
+  VirtRegMap(const VirtRegMap &) = delete;
+  VirtRegMap &operator=(const VirtRegMap &) = delete;
+  VirtRegMap(VirtRegMap &&) = default;
+
+  void init(MachineFunction &MF);
+
+  MachineFunction &getMachineFunction() const {
+    assert(MF && "getMachineFunction called before runOnMachineFunction");
+    return *MF;
+  }
 
-    /// Virt2StackSlotMap - This is virtual register to stack slot
-    /// mapping. Each spilled virtual register has an entry in it
-    /// which corresponds to the stack slot this register is spilled
-    /// at.
-    IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
+  MachineRegisterInfo &getRegInfo() const { return *MRI; }
+  const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
 
-    /// Virt2SplitMap - This is virtual register to splitted virtual register
-    /// mapping.
-    IndexedMap<Register, VirtReg2IndexFunctor> Virt2SplitMap;
+  void grow();
 
-    /// Virt2ShapeMap - For X86 AMX register whose register is bound shape
-    /// information.
-    DenseMap<Register, ShapeT> Virt2ShapeMap;
+  /// returns true if the specified virtual register is
+  /// mapped to a physical register
+  bool hasPhys(Register virtReg) const { return getPhys(virtReg).isValid(); }
 
-    /// createSpillSlot - Allocate a spill slot for RC from MFI.
-    unsigned createSpillSlot(const TargetRegisterClass *RC);
+  /// returns the physical register mapped to the specified
+  /// virtual register
+  MCRegister getPhys(Register virtReg) const {
+    assert(virtReg.isVirtual());
+    return Virt2PhysMap[virtReg];
+  }
 
-  public:
-    static char ID;
+  /// creates a mapping for the specified virtual register to
+  /// the specified physical register
+  void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
 
-    static constexpr int NO_STACK_SLOT = INT_MAX;
+  bool isShapeMapEmpty() const { return Virt2ShapeMap.empty(); }
 
-    VirtRegMap() : MachineFunctionPass(ID), Virt2StackSlotMap(NO_STACK_SLOT) {}
-    VirtRegMap(const VirtRegMap &) = delete;
-    VirtRegMap &operator=(const VirtRegMap &) = delete;
+  bool hasShape(Register virtReg) const {
+    return Virt2ShapeMap.contains(virtReg);
+  }
 
-    bool runOnMachineFunction(MachineFunction &MF) override;
+  ShapeT getShape(Register virtReg) const {
+    assert(virtReg.isVirtual());
+    return Virt2ShapeMap.lookup(virtReg);
+  }
 
-    void getAnalysisUsage(AnalysisUsage &AU) const override {
-      AU.setPreservesAll();
-      MachineFunctionPass::getAnalysisUsage(AU);
-    }
+  void assignVirt2Shape(Register virtReg, ShapeT shape) {
+    Virt2ShapeMap[virtReg] = shape;
+  }
 
-    MachineFunction &getMachineFunction() const {
-      assert(MF && "getMachineFunction called before runOnMachineFunction");
-      return *MF;
-    }
+  /// clears the specified virtual register's, physical
+  /// register mapping
+  void clearVirt(Register virtReg) {
+    assert(virtReg.isVirtual());
+    assert(Virt2PhysMap[virtReg] &&
+           "attempt to clear a not assigned virtual register");
+    Virt2PhysMap[virtReg] = MCRegister();
+  }
 
-    MachineRegisterInfo &getRegInfo() const { return *MRI; }
-    const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
+  /// clears all virtual to physical register mappings
+  void clearAllVirt() {
+    Virt2PhysMap.clear();
+    grow();
+  }
 
-    void grow();
+  /// returns true if VirtReg is assigned to its preferred physreg.
+  bool hasPreferredPhys(Register VirtReg) const;
 
-    /// returns true if the specified virtual register is
-    /// mapped to a physical register
-    bool hasPhys(Register virtReg) const { return getPhys(virtReg).isValid(); }
+  /// returns true if VirtReg has a known preferred register.
+  /// This returns false if VirtReg has a preference that is a virtual
+  /// register that hasn't been assigned yet.
+  bool hasKnownPreference(Register VirtReg) const;
 
-    /// returns the physical register mapped to the specified
-    /// virtual register
-    MCRegister getPhys(Register virtReg) const {
-      assert(virtReg.isVirtual());
-      return Virt2PhysMap[virtReg];
+  /// records virtReg is a split live interval from SReg.
+  void setIsSplitFromReg(Register virtReg, Register SReg) {
+    Virt2SplitMap[virtReg] = SReg;
+    if (hasShape(SReg)) {
+      Virt2ShapeMap[virtReg] = getShape(SReg);
     }
+  }
 
-    /// creates a mapping for the specified virtual register to
-    /// the specified physical register
-    void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
+  /// returns the live interval virtReg is split from.
+  Register getPreSplitReg(Register virtReg) const {
+    return Virt2SplitMap[virtReg];
+  }
 
-    bool isShapeMapEmpty() const { return Virt2ShapeMap.empty(); }
+  /// getOriginal - Return the original virtual register that VirtReg descends
+  /// from through splitting.
+  /// A register that was not created by splitting is its own original.
+  /// This operation is idempotent.
+  Register getOriginal(Register VirtReg) const {
+    Register Orig = getPreSplitReg(VirtReg);
+    return Orig ? Orig : VirtReg;
+  }
 
-    bool hasShape(Register virtReg) const {
-      return Virt2ShapeMap.contains(virtReg);
-    }
+  /// returns true if the specified virtual register is not
+  /// mapped to a stack slot or rematerialized.
+  bool isAssignedReg(Register virtReg) const {
+    if (getStackSlot(virtReg) == NO_STACK_SLOT)
+      return true;
+    // Split register can be assigned a physical register as well as a
+    // stack slot or remat id.
+    return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg]);
+  }
 
-    ShapeT getShape(Register virtReg) const {
-      assert(virtReg.isVirtual());
-      return Virt2ShapeMap.lookup(virtReg);
-    }
+  /// returns the stack slot mapped to the specified virtual
+  /// register
+  int getStackSlot(Register virtReg) const {
+    assert(virtReg.isVirtual());
+    return Virt2StackSlotMap[virtReg];
+  }
 
-    void assignVirt2Shape(Register virtReg, ShapeT shape) {
-      Virt2ShapeMap[virtReg] = shape;
-    }
+  /// create a mapping for the specifed virtual register to
+  /// the next available stack slot
+  int assignVirt2StackSlot(Register virtReg);
 
-    /// clears the specified virtual register's, physical
-    /// register mapping
-    void clearVirt(Register virtReg) {
-      assert(virtReg.isVirtual());
-      assert(Virt2PhysMap[virtReg] &&
-             "attempt to clear a not assigned virtual register");
-      Virt2PhysMap[virtReg] = MCRegister();
-    }
+  /// create a mapping for the specified virtual register to
+  /// the specified stack slot
+  void assignVirt2StackSlot(Register virtReg, int SS);
 
-    /// clears all virtual to physical register mappings
-    void clearAllVirt() {
-      Virt2PhysMap.clear();
-      grow();
-    }
+  void print(raw_ostream &OS, const Module *M = nullptr) const;
+  void dump() const;
+};
 
-    /// returns true if VirtReg is assigned to its preferred physreg.
-    bool hasPreferredPhys(Register VirtReg) const;
+inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
+  VRM.print(OS);
+  return OS;
+}
 
-    /// returns true if VirtReg has a known preferred register.
-    /// This returns false if VirtReg has a preference that is a virtual
-    /// register that hasn't been assigned yet.
-    bool hasKnownPreference(Register VirtReg) const;
+class VirtRegMapWrapperLegacy : public MachineFunctionPass {
+  VirtRegMap VRM;
 
-    /// records virtReg is a split live interval from SReg.
-    void setIsSplitFromReg(Register virtReg, Register SReg) {
-      Virt2SplitMap[virtReg] = SReg;
-      if (hasShape(SReg)) {
-        Virt2ShapeMap[virtReg] = getShape(SReg);
-      }
-    }
+public:
+  static char ID;
 
-    /// returns the live interval virtReg is split from.
-    Register getPreSplitReg(Register virtReg) const {
-      return Virt2SplitMap[virtReg];
-    }
+  VirtRegMapWrapperLegacy() : MachineFunctionPass(ID) {}
 
-    /// getOriginal - Return the original virtual register that VirtReg descends
-    /// from through splitting.
-    /// A register that was not created by splitting is its own original.
-    /// This operation is idempotent.
-    Register getOriginal(Register VirtReg) const {
-      Register Orig = getPreSplitReg(VirtReg);
-      return Orig ? Orig : VirtReg;
-    }
+  void print(raw_ostream &OS, const Module *M = nullptr) const override {
+    VRM.print(OS, M);
+  }
 
-    /// returns true if the specified virtual register is not
-    /// mapped to a stack slot or rematerialized.
-    bool isAssignedReg(Register virtReg) const {
-      if (getStackSlot(virtReg) == NO_STACK_SLOT)
-        return true;
-      // Split register can be assigned a physical register as well as a
-      // stack slot or remat id.
-      return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg]);
-    }
+  VirtRegMap &getVRM() { return VRM; }
+  const VirtRegMap &getVRM() const { return VRM; }
 
-    /// returns the stack slot mapped to the specified virtual
-    /// register
-    int getStackSlot(Register virtReg) const {
-      assert(virtReg.isVirtual());
-      return Virt2StackSlotMap[virtReg];
-    }
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    VRM.init(MF);
+    return false;
+  }
 
-    /// create a mapping for the specifed virtual register to
-    /// the next available stack slot
-    int assignVirt2StackSlot(Register virtReg);
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+};
 
-    /// create a mapping for the specified virtual register to
-    /// the specified stack slot
-    void assignVirt2StackSlot(Register virtReg, int SS);
+class VirtRegMapAnalysis : public AnalysisInfoMixin<VirtRegMapAnalysis> {
+  friend AnalysisInfoMixin<VirtRegMapAnalysis>;
+  static AnalysisKey Key;
 
-    void print(raw_ostream &OS, const Module* M = nullptr) const override;
-    void dump() const;
-  };
+public:
+  using Result = VirtRegMap;
 
-  inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
-    VRM.print(OS);
-    return OS;
-  }
+  VirtRegMap run(MachineFunction &MF, MachineFunctionAnalysisManager &MAM);
+};
+
+class VirtRegMapPrinterPass : public PassInfoMixin<VirtRegMapPrinterPass> {
+  raw_ostream &OS;
 
+public:
+  explicit VirtRegMapPrinterPass(raw_ostream &OS) : OS(OS) {}
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
+};
 } // end llvm namespace
 
 #endif // LLVM_CODEGEN_VIRTREGMAP_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index e50cb0dd7541a..537166c393c7f 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -315,7 +315,7 @@ void initializeUnpackMachineBundlesPass(PassRegistry &);
 void initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
 void initializeUnreachableMachineBlockElimPass(PassRegistry &);
 void initializeVerifierLegacyPassPass(PassRegistry &);
-void initializeVirtRegMapPass(PassRegistry &);
+void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
 void initializeVirtRegRewriterPass(PassRegistry &);
 void initializeWasmEHPreparePass(PassRegistry &);
 void initializeWinEHPreparePass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 4e44d0312ede4..d92fd19a1882c 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -109,6 +109,7 @@ MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
 MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
 MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
 MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis())
 // MACHINE_FUNCTION_ANALYSIS("live-stacks", LiveStacksPass())
 // MACHINE_FUNCTION_ANALYSIS("edge-bundles", EdgeBundlesAnalysis())
 // MACHINE_FUNCTION_ANALYSIS("lazy-machine-bfi",
@@ -150,6 +151,7 @@ MACHINE_FUNCTION_PASS("print<machine-loops>", MachineLoopPrinterPass(dbgs()))
 MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>",
                       MachinePostDominatorTreePrinterPass(dbgs()))
 MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(dbgs()))
 MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
                       RequireAllMachineFunctionPropertiesPass())
 MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 2d7f351de54ec..66fc5de299ae4 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -138,7 +138,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeUnpackMachineBundlesPass(Registry);
   initializeUnreachableBlockElimLegacyPassPass(Registry);
   initializeUnreachableMachineBlockElimPass(Registry);
-  initializeVirtRegMapPass(Registry);
+  initializeVirtRegMapWrapperLegacyPass(Registry);
   initializeVirtRegRewriterPass(Registry);
   initializeWasmEHPreparePass(Registry);
   initializeWinEHPreparePass(Registry);
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index c8c722359a4c4..a0e8b0e4f9cc1 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -39,7 +39,7 @@ char LiveRegMatrix::ID = 0;
 INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
                       "Live Register Matrix", false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
                     "Live Register Matrix", false, false)
 
@@ -48,14 +48,14 @@ LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID) {}
 void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
   AU.addRequiredTransitive<LiveIntervalsWrapperPass>();
-  AU.addRequiredTransitive<VirtRegMap>();
+  AU.addRequiredTransitive<VirtRegMapWrapperLegacy>();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
   TRI = MF.getSubtarget().getRegisterInfo();
   LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-  VRM = &getAnalysis<VirtRegMap>();
+  VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
 
   unsigned NumRegUnits = TRI->getNumRegUnits();
   if (NumRegUnits != Matrix.size())
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index 046784c386e30..07d7e212adfce 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -139,7 +139,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveStacks)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
 INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
@@ -191,8 +191,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addPreservedID(MachineDominatorsID);
   AU.addRequired<MachineLoopInfoWrapperPass>();
   AU.addPreserved<MachineLoopInfoWrapperPass>();
-  AU.addRequired<VirtRegMap>();
-  AU.addPreserved<VirtRegMap>();
+  AU.addRequired<VirtRegMapWrapperLegacy>();
+  AU.addPreserved<VirtRegMapWrapperLegacy>();
   AU.addRequired<LiveRegMatrix>();
   AU.addPreserved<LiveRegMatrix>();
   MachineFunctionPass::getAnalysisUsage(AU);
@@ -310,7 +310,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
                     << "********** Function: " << mf.getName() << '\n');
 
   MF = &mf;
-  RegAllocBase::init(getAnalysis<VirtRegMap>(),
+  RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
                      getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
                      getAnalysis<LiveRegMatrix>());
   VirtRegAuxInfo VRAI(
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 8cfd2192de460..2c9bb0aa14557 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -162,7 +162,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
 INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
 INITIALIZE_PASS_DEPENDENCY(SpillPlacement)
@@ -215,8 +215,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addPreserved<MachineDominatorTreeWrapperPass>();
   AU.addRequired<MachineLoopInfoWrapperPass>();
   AU.addPreserved<MachineLoopInfoWrapperPass>();
-  AU.addRequired<VirtRegMap>();
-  AU.addPreserved<VirtRegMap>();
+  AU.addRequired<VirtRegMapWrapperLegacy>();
+  AU.addPreserved<VirtRegMapWrapperLegacy>();
   AU.addRequired<LiveRegMatrix>();
   AU.addPreserved<LiveRegMatrix>();
   AU.addRequired<EdgeBundles>();
@@ -2716,7 +2716,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
   if (VerifyEnabled)
     MF->verify(this, "Before greedy register allocator", &errs());
 
-  RegAllocBase::init(getAnalysis<VirtRegMap>(),
+  RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
                      getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
                      getAnalysis<LiveRegMatrix>());
 
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index e6f28d6af29fa..b1301825be1ca 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -123,7 +123,7 @@ class RegAllocPBQP : public MachineFunctionPass {
     initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry());
     initializeLiveIntervalsWrapperPassPass(*PassRegistry::getPassRegistry());
     initializeLiveStacksPass(*PassRegistry::getPassRegistry());
-    initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
+    initializeVirtRegMapWrapperLegacyPass(*PassRegistry::getPassRegistry());
   }
 
   /// Return the pass name.
@@ -559,8 +559,8 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
   au.addPreserved<MachineLoopInfoWrapperPass>();
   au.addRequired<MachineDominatorTreeWrapperPass>();
   au.addPreserved<MachineDominatorTreeWrapperPass>();
-  au.addRequired<VirtRegMap>();
-  au.addPreserved<VirtRegMap>();
+  au.addRequired<VirtRegMapWrapperLegacy>();
+  au.addPreserved<VirtRegMapWrapperLegacy>();
   MachineFunctionPass::getAnalysisUsage(au);
 }
 
@@ -795,7 +795,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
   MachineBlockFrequencyInfo &MBFI =
       getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
 
-  VirtRegMap &VRM = getAnalysis<VirtRegMap>();
+  VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
 
   PBQPVirtRegAuxInfo VRAI(
       MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index a548bf665bcea..46253b1743d97 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -56,11 +56,12 @@ STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
 //  VirtRegMap implementation
 //===----------------------------------------------------------------------===//
 
-char VirtRegMap::ID = 0;
+char VirtRegMapWrapperLegacy::ID = 0;
 
-INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
+INITIALIZE_PASS(VirtRegMapWrapperLegacy, "virtregmap", "Virtual Register Map",
+                false, false)
 
-bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
+void VirtRegMap::init(MachineFunction &mf) {
   MRI = &mf.getRegInfo();
   TII = mf.getSubtarget().getInstrInfo();
   TRI = mf.getSubtarget().getRegisterInfo();
@@ -72,7 +73,6 @@ bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
   Virt2ShapeMap.clear();
 
   grow();
-  return false;
 }
 
 void VirtRegMap::grow() {
@@ -169,6 +169,22 @@ LLVM_DUMP_METHOD void VirtRegMap::dump() const {
 }
 #endif
 
+AnalysisKey VirtRegMapAnalysis::Key;
+
+PreservedAnalyses
+VirtRegMapPrinterPass::run(MachineFunction &MF,
+                           MachineFunctionAnalysisManager &MFAM) {
+  OS << MFAM.getResult<VirtRegMapAnalysis>(MF);
+  return PreservedAnalyses::all();
+}
+
+VirtRegMap VirtRegMapAnalysis::run(MachineFunction &MF,
+                                   MachineFunctionAnalysisManager &MAM) {
+  VirtRegMap VRM;
+  VRM.init(MF);
+  return VRM;
+}
+
 //===----------------------------------------------------------------------===//
 //                              VirtRegRewriter
 //===----------------------------------------------------------------------===//
@@ -232,7 +248,7 @@ INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
                     "Virtual Register Rewriter", false, false)
 
@@ -245,7 +261,7 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<LiveDebugVariables>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();
-  AU.addRequired<VirtRegMap>();
+  AU.addRequired<VirtRegMapWrapperLegacy>();
 
   if (!ClearVirtRegs)
     AU.addPreserved<LiveDebugVariables>();
@@ -260,7 +276,7 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
   MRI = &MF->getRegInfo();
   Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
   LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-  VRM = &getAnalysis<VirtRegMap>();
+  VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
   DebugVars = &getAnalysis<LiveDebugVariables>();
   LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
                     << "********** Function: " << MF->getName() << '\n');
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index be0a0f3fa97b4..c2aef42780321 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -126,6 +126,7 @@
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TwoAddressInstructionPass.h"
 #include "llvm/CodeGen/TypePromotion.h"
+#include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
 #include "llvm/CodeGen/WinEHPrepare.h"
 #include "llvm/IR/DebugInfo.h"
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
index 18ffd8820f95e..40af37141fe61 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -49,7 +49,7 @@ class GCNNSAReassign : public MachineFunctionPass {
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<LiveIntervalsWrapperPass>();
-    AU.addRequired<VirtRegMap>();
+    AU.addRequired<VirtRegMapWrapperLegacy>();
     AU.addRequired<LiveRegMatrix>();
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
@@ -95,7 +95,7 @@ class GCNNSAReassign : public MachineFunctionPass {
 INITIALIZE_PASS_BEGIN(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
                       false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
 INITIALIZE_PASS_END(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
                     false, false)
@@ -242,7 +242,7 @@ bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
 
   MRI = &MF.getRegInfo();
   TRI = ST->getRegisterInfo();
-  VRM = &getAnalysis<VirtRegMap>();
+  VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
   LRM = &getAnalysis<LiveRegMatrix>();
   LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 822336ebaf5dc..4afefa3d9b245 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -95,7 +95,7 @@ char SILowerSGPRSpillsLegacy::ID = 0;
 INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
                       "SI lower SGPR spill instructions", false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
 INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
                     "SI lower SGPR spill instructions", false, false)
diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
index 7bff58c7aa86c..c663820311b8c 100644
--- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
@@ -64,7 +64,7 @@ class SILowerWWMCopies : public MachineFunctionPass {
 INITIALIZE_PASS_BEGIN(SILowerWWMCopies, DEBUG_TYPE, "SI Lower WWM Copies",
                       false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_END(SILowerWWMCopies, DEBUG_TYPE, "SI Lower WWM Copies", false,
                     false)
 
@@ -105,7 +105,8 @@ bool SILowerWWMCopies::runOnMachineFunction(MachineFunction &MF) {
   LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
   auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
   Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
-  VRM = getAnalysisIfAvailable<VirtRegMap>();
+  auto *VRMWrapper = getAnalysisIfAvailable<VirtRegMapWrapperLegacy>();
+  VRM = VRMWrapper ? &VRMWrapper->getVRM() : nullptr;
   TRI = ST.getRegisterInfo();
   MRI = &MF.getRegInfo();
 
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index b17fb7e70826b..211f3f11006ff 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -60,7 +60,7 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<LiveIntervalsWrapperPass>();
-    AU.addRequired<VirtRegMap>();
+    AU.addRequired<VirtRegMapWrapperLegacy>();
     AU.addRequired<LiveRegMatrix>();
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
@@ -76,7 +76,7 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
 INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE,
                 "SI Pre-allocate WWM Registers", false, false)
 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
 INITIALIZE_PASS_END(SIPreAllocateWWMRegs, DEBUG_TYPE,
                 "SI Pre-allocate WWM Registers", false, false)
@@ -195,7 +195,7 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
 
   LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
   Matrix = &getAnalysis<LiveRegMatrix>();
-  VRM = &getAnalysis<VirtRegMap>();
+  VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
 
   RegClassInfo.runOnMachineFunction(MF);
 
diff --git a/llvm/lib/Target/X86/X86TileConfig.cpp b/llvm/lib/Target/X86/X86TileConfig.cpp
index 30295e9929c6a..2250c3912a90d 100644
--- a/llvm/lib/Target/X86/X86TileConfig.cpp
+++ b/llvm/lib/Target/X86/X86TileConfig.cpp
@@ -50,7 +50,7 @@ struct X86TileConfig : public MachineFunctionPass {
   /// X86TileConfig analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
-    AU.addRequired<VirtRegMap>();
+    AU.addRequired<VirtRegMapWrapperLegacy>();
     AU.addRequired<LiveIntervalsWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
@@ -72,7 +72,7 @@ char X86TileConfig::ID = 0;
 
 INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure",
                       false, false)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
 INITIALIZE_PASS_END(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false,
                     false)
 
@@ -87,7 +87,7 @@ bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
   const TargetInstrInfo *TII = ST.getInstrInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-  VirtRegMap &VRM = getAnalysis<VirtRegMap>();
+  VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
 
   if (VRM.isShapeMapEmpty())
     return false;