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[RISCV] Add lowerVECTOR_SHUFFLEAsCONCAT_VECTORS. #109948

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[RISCV] Add lowerVECTOR_SHUFFLEAsCONCAT_VECTORS. #109948

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a34cd59
[RISCV] Pre-commit test.
HanKuanChen Sep 25, 2024
01d6011
[RISCV] Add lowerVECTOR_SHUFFLEAsCONCAT_VECTORS.
HanKuanChen Sep 25, 2024
3c9519d
[RISCV] Clean useless IR.
HanKuanChen Sep 25, 2024
7d5156f
[RISCV] Apply comment.
HanKuanChen Sep 25, 2024
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34 changes: 34 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5130,6 +5130,37 @@ static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN,
return DAG.getBitcast(VT, Rotate);
}

// e.g.,
// t10 = insert_subvector undef:v16i32, t4, Constant:i64<0>
// vector_shuffle<0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3> t10, undef:v16i32
// ->
// concat_vectors t4, t4, t4, t4
static SDValue
lowerVECTOR_SHUFFLEAsCONCAT_VECTORS(ShuffleVectorSDNode *SVN, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(SVN->getOperand(1).isUndef());
SDValue V1 = SVN->getOperand(0);
if (V1.getOpcode() != ISD::INSERT_SUBVECTOR)
return SDValue();
if (!V1.getOperand(0).isUndef() || V1.getConstantOperandVal(2) != 0)
return SDValue();
SDValue InsertValue = V1.getOperand(1);
MVT SubVecVT = InsertValue.getSimpleValueType();
unsigned SubVecNumElements = SubVecVT.getVectorNumElements();
ArrayRef<int> Mask = SVN->getMask();
if (Mask.size() % SubVecNumElements != 0)
return SDValue();
SmallVector<int> RepeatedPattern(
createSequentialMask(0, SubVecNumElements, 0));
// Check the Mask repeatedly uses the same subvector.
for (unsigned I = 0; I != Mask.size(); I += SubVecNumElements)
if (!Mask.slice(I, SubVecNumElements).equals(RepeatedPattern))
return SDValue();
SDLoc DL(SVN);
SmallVector<SDValue> Ops(Mask.size() / SubVecNumElements, InsertValue);
return DAG.getNode(ISD::CONCAT_VECTORS, DL, SVN->getSimpleValueType(0), Ops);
}

// If compiling with an exactly known VLEN, see if we can split a
// shuffle on m2 or larger into a small number of m1 sized shuffles
// which write each destination registers exactly once.
Expand Down Expand Up @@ -5432,6 +5463,9 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget))
return V;

if (SDValue V = lowerVECTOR_SHUFFLEAsCONCAT_VECTORS(SVN, DAG, Subtarget))
return V;

if (VT.getScalarSizeInBits() == 8 &&
any_of(Mask, [&](const auto &Idx) { return Idx > 255; })) {
// On such a vector we're unable to use i8 as the index type.
Expand Down
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat-vectors.ll
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@@ -0,0 +1,32 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv64 -mattr=+v -riscv-v-vector-bits-min=512 -verify-machineinstrs < %s | FileCheck %s

define <16 x float> @test1(<8 x float> %0) {
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@topperc topperc Sep 26, 2024 •
edited
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InstCombine already flattens both of these tests. Do you have other examples?

define <16 x float> @test1(<8 x float> %0) {
entry:
  %1 = shufflevector <8 x float> %0, <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <16 x float> %1
}

define <16 x i32> @test2(<4 x i32> %0) {
entry:
  %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  ret <16 x i32> %1
}

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@HanKuanChen HanKuanChen Sep 26, 2024

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That is true. But I want to make sure INSERT_SUBVECTOR + VECTOR_SHUFFLE can be folded into CONCAT_VECTORS. SLP will generate the code like this.

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@topperc topperc Sep 26, 2024

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InstCombine should run after SLP. Do you have examples where InstCombine isn't cleaning it up? If you do, we should investigate InstCombine first.

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@HanKuanChen HanKuanChen Sep 26, 2024

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No for now.

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@topperc topperc Sep 26, 2024

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This also doesn't seem like a RISC-V specific optimization.

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@lukel97 lukel97 Sep 26, 2024

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I was thinking that as well. It looks like GISel canonicalizes shuffles to concats: https://reviews.llvm.org/D69149

I didn't notice any codegen changes with this patch when building SPEC or the test suite so I presume that's InstCombine already taking care of this.

; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 8
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%1 = call <16 x float> @llvm.vector.insert.v16f32.v8f32(<16 x float> poison, <8 x float> %0, i64 0)
%2 = shufflevector <16 x float> %1, <16 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <16 x float> %2
}

define <16 x i32> @test2(<4 x i32> %0) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 8
; CHECK-NEXT: ret
entry:
%1 = call <16 x i32> @llvm.vector.insert.v16i32.v4i32(<16 x i32> poison, <4 x i32> %0, i64 0)
%2 = shufflevector <16 x i32> %1, <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
ret <16 x i32> %2
}
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