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Merged
merged 2 commits into from
Oct 3, 2024
Merged

[Xtensa] Implement volatile load/store. #110292

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1db96f6
[Xtensa] Implement volatile load/store.
andreisfr Sep 27, 2024
4918c04
[Xtensa] Minor fix in test.
andreisfr Oct 3, 2024
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17 changes: 17 additions & 0 deletions llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@

#include "XtensaISelLowering.h"
#include "XtensaConstantPoolValue.h"
#include "XtensaInstrInfo.h"
#include "XtensaSubtarget.h"
#include "XtensaTargetMachine.h"
#include "llvm/CodeGen/CallingConvLower.h"
Expand Down Expand Up @@ -1104,10 +1105,26 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
MachineInstr &MI, MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
const XtensaInstrInfo &TII = *Subtarget.getInstrInfo();

switch (MI.getOpcode()) {
case Xtensa::SELECT:
return emitSelectCC(MI, MBB);
case Xtensa::S8I:
case Xtensa::S16I:
case Xtensa::S32I:
case Xtensa::L8UI:
case Xtensa::L16SI:
case Xtensa::L16UI:
case Xtensa::L32I: {
// Insert memory wait instruction "memw" before volatile load/store as it is
// implemented in gcc. If memoperands is empty then assume that it aslo
// maybe volatile load/store and insert "memw".
if (MI.memoperands_empty() || (*MI.memoperands_begin())->isVolatile()) {
BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW));
}
return MBB;
}
default:
llvm_unreachable("Unexpected instr type to insert");
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Xtensa/XtensaInstrInfo.td
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Expand Up @@ -195,7 +195,7 @@ def SSAI : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins uimm5:$imm),
//===----------------------------------------------------------------------===//

// Load instructions
let mayLoad = 1 in {
let mayLoad = 1, usesCustomInserter = 1 in {

class Load_RRI8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
ComplexPattern addrOp, Operand memOp>
Expand All @@ -216,7 +216,7 @@ def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>;
def L32I : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>;

// Store instructions
let mayStore = 1 in {
let mayStore = 1, usesCustomInserter = 1 in {
class Store_II8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
ComplexPattern addrOp, Operand memOp>
: RRI8_Inst<0x02, (outs), (ins AR:$t, memOp:$addr),
Expand Down
25 changes: 12 additions & 13 deletions llvm/test/CodeGen/Xtensa/blockaddress.ll
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@@ -1,22 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=xtensa < %s | FileCheck %s

@addr = global ptr null

define void @test_blockaddress() {

store volatile ptr blockaddress(@test_blockaddress, %block), ptr @addr
; CHECK: .literal_position
; CHECK-NEXT: .literal .LCPI0_0, addr
; CHECK-NEXT: .literal .LCPI0_1, .Ltmp0
; CHECK-LABEL: test_blockaddress:
; CHECK: # %bb.0:
; CHECK-NEXT: l32r a8, .LCPI0_0
; CHECK-NEXT: l32r a9, .LCPI0_1
; CHECK-NEXT: s32i a9, a8, 0
; CHECK-NEXT: l32i a8, a8, 0
; CHECK-NEXT: jx a8
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: .LBB0_1:
; CHECK: l32r a8, .LCPI0_0
; CHECK-NEXT: l32r a9, .LCPI0_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a9, a8, 0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 0
; CHECK-NEXT: jx a8
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: .LBB0_1: # %block
; CHECK-NEXT: ret
store volatile ptr blockaddress(@test_blockaddress, %block), ptr @addr

%val = load volatile ptr, ptr @addr
indirectbr ptr %val, [label %block]
Expand Down
176 changes: 176 additions & 0 deletions llvm/test/CodeGen/Xtensa/volatile.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,176 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
; RUN: | FileCheck %s

@x_i8 = common dso_local global i8 0, align 8
@y_i8 = common dso_local global i8 0, align 8
@x_i16 = common dso_local global i16 0, align 8
@y_i16 = common dso_local global i16 0, align 8
@x_i32 = common dso_local global i32 0, align 8
@y_i32 = common dso_local global i32 0, align 8
@x_i64 = common dso_local global i64 0, align 8
@y_i64 = common dso_local global i64 0, align 8
@x_float = common dso_local global float 0.0, align 8
@y_float = common dso_local global float 0.0, align 8
@x_double = common dso_local global double 0.0, align 8
@y_double = common dso_local global double 0.0, align 8
@x_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 8
@y_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 8

define void @test() {
; CHECK-LABEL: test:
; CHECK: l32r a8, .LCPI0_0
; CHECK-NEXT: memw
; CHECK-NEXT: l8ui a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI0_1
; CHECK-NEXT: memw
; CHECK-NEXT: s8i a8, a9, 0
; CHECK-NEXT: l32r a8, .LCPI0_2
; CHECK-NEXT: memw
; CHECK-NEXT: l16ui a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI0_3
; CHECK-NEXT: memw
; CHECK-NEXT: s16i a8, a9, 0
; CHECK-NEXT: l32r a8, .LCPI0_4
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI0_5
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a9, 0
; CHECK-NEXT: ret

entry:
%0 = load volatile i8, ptr @x_i8, align 4
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@arsenm arsenm Sep 29, 2024

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Named values in tests

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@andreisfr andreisfr Oct 2, 2024

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Fixed

store volatile i8 %0, ptr @y_i8, align 4
%1 = load volatile i16, ptr @x_i16, align 4
store volatile i16 %1, ptr @y_i16, align 4
%2 = load volatile i32, ptr @x_i32, align 4
store volatile i32 %2, ptr @y_i32, align 4
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@arsenm arsenm Sep 29, 2024

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Split each of these into its own test function?

Also test other types? i64, float, double, vectors, exotic types?

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@andreisfr andreisfr Oct 2, 2024

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Thank you for comment. I added tests with other types.

ret void
}


define void @test_i8() {
; CHECK-LABEL: test_i8:
; CHECK: l32r a8, .LCPI1_0
; CHECK-NEXT: memw
; CHECK-NEXT: l8ui a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI1_1
; CHECK-NEXT: memw
; CHECK-NEXT: s8i a8, a9, 0
; CHECK-NEXT: ret
entry:
%a = load volatile i8, ptr @x_i8, align 4
store volatile i8 %a, ptr @y_i8, align 4
ret void
}

define void @test_i16() {
; CHECK-LABEL: test_i16:
; CHECK: l32r a8, .LCPI2_0
; CHECK-NEXT: memw
; CHECK-NEXT: l16ui a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI2_1
; CHECK-NEXT: memw
; CHECK-NEXT: s16i a8, a9, 0
; CHECK-NEXT: ret
entry:
%a = load volatile i16, ptr @x_i16, align 4
store volatile i16 %a, ptr @y_i16, align 4
ret void
}

define void @test_i32() {
; CHECK-LABEL: test_i32:
; CHECK: l32r a8, .LCPI3_0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI3_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a9, 0
; CHECK-NEXT: ret
entry:
%a = load volatile i32, ptr @x_i32, align 4
store volatile i32 %a, ptr @y_i32, align 4
ret void
}

define void @test_i64() {
; CHECK-LABEL: test_i64:
; CHECK: l32r a8, .LCPI4_0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a9, a8, 0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 4
; CHECK-NEXT: l32r a10, .LCPI4_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a10, 4
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a9, a10, 0
; CHECK-NEXT: ret
entry:
%a = load volatile i64, ptr @x_i64, align 4
store volatile i64 %a, ptr @y_i64, align 4
ret void
}

define void @test_float() {
; CHECK-LABEL: test_float:
; CHECK: l32r a8, .LCPI5_0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 0
; CHECK-NEXT: l32r a9, .LCPI5_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a9, 0
; CHECK-NEXT: ret
entry:
%a = load volatile float, ptr @x_float, align 4
store volatile float %a, ptr @y_float, align 4
ret void
}

define void @test_double() {
; CHECK-LABEL: test_double:
; CHECK: l32r a8, .LCPI6_0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a9, a8, 0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 4
; CHECK-NEXT: l32r a10, .LCPI6_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a10, 4
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a9, a10, 0
; CHECK-NEXT: ret
entry:
%a = load volatile double, ptr @x_double, align 4
store volatile double %a, ptr @y_double, align 4
ret void
}

define void @test_vec() {
; CHECK-LABEL: test_vec:
; CHECK: l32r a8, .LCPI7_0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a9, a8, 0
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a10, a8, 4
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a11, a8, 8
; CHECK-NEXT: memw
; CHECK-NEXT: l32i a8, a8, 12
; CHECK-NEXT: l32r a7, .LCPI7_1
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a8, a7, 12
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a11, a7, 8
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a10, a7, 4
; CHECK-NEXT: memw
; CHECK-NEXT: s32i a9, a7, 0
; CHECK-NEXT: ret
entry:
%a = load volatile <4 x i32>, ptr @x_vec, align 4
store volatile <4 x i32> %a, ptr @y_vec, align 4
ret void
}
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