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[llvm] Mark win x64 SEH pseudo instruction as meta instructions #110889

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Merged
merged 1 commit into from
Oct 2, 2024
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[llvm] Mark win x64 SEH pseudo instruction as meta instructions #110889

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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86InstrCompiler.td
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Original file line number Diff line number Diff line change
Expand Up @@ -235,7 +235,7 @@ let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
//===----------------------------------------------------------------------===//
// Pseudo instructions used by unwind info.
//
let isPseudo = 1, SchedRW = [WriteSystem] in {
let isPseudo = 1, isMeta = 1, SchedRW = [WriteSystem] in {
def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
"#SEH_PushReg $reg", []>;
def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; ENABLE-NEXT: .seh_pushreg %rbx
; ENABLE-NEXT: .seh_endprologue
; ENABLE-NEXT: testl %ecx, %ecx
; ENABLE-NEXT: je .LBB0_4
; ENABLE-NEXT: je .LBB0_5
; ENABLE-NEXT: # %bb.1: # %for.preheader
; ENABLE-NEXT: #APP
; ENABLE-NEXT: nop
Expand All @@ -38,11 +38,11 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; ENABLE-NEXT: nop
; ENABLE-NEXT: #NO_APP
; ENABLE-NEXT: shll $3, %eax
; ENABLE-NEXT: jmp .LBB0_5
; ENABLE-NEXT: .LBB0_4: # %if.else
; ENABLE-NEXT: popq %rbx
; ENABLE-NEXT: retq
; ENABLE-NEXT: .LBB0_5: # %if.else
; ENABLE-NEXT: movl %edx, %eax
; ENABLE-NEXT: addl %edx, %eax
; ENABLE-NEXT: .LBB0_5: # %if.end
; ENABLE-NEXT: popq %rbx
; ENABLE-NEXT: retq
; ENABLE-NEXT: .seh_endproc
Expand All @@ -53,7 +53,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: .seh_pushreg %rbx
; DISABLE-NEXT: .seh_endprologue
; DISABLE-NEXT: testl %ecx, %ecx
; DISABLE-NEXT: je .LBB0_4
; DISABLE-NEXT: je .LBB0_5
; DISABLE-NEXT: # %bb.1: # %for.preheader
; DISABLE-NEXT: #APP
; DISABLE-NEXT: nop
Expand All @@ -74,11 +74,11 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: nop
; DISABLE-NEXT: #NO_APP
; DISABLE-NEXT: shll $3, %eax
; DISABLE-NEXT: jmp .LBB0_5
; DISABLE-NEXT: .LBB0_4: # %if.else
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .LBB0_5: # %if.else
; DISABLE-NEXT: movl %edx, %eax
; DISABLE-NEXT: addl %edx, %eax
; DISABLE-NEXT: .LBB0_5: # %if.end
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .seh_endproc
Expand Down Expand Up @@ -157,7 +157,7 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: .seh_pushreg %rbx
; DISABLE-NEXT: .seh_endprologue
; DISABLE-NEXT: testl %ecx, %ecx
; DISABLE-NEXT: je .LBB1_4
; DISABLE-NEXT: je .LBB1_5
; DISABLE-NEXT: # %bb.1: # %for.preheader
; DISABLE-NEXT: #APP
; DISABLE-NEXT: nop
Expand All @@ -178,11 +178,11 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: nop
; DISABLE-NEXT: #NO_APP
; DISABLE-NEXT: shll $3, %eax
; DISABLE-NEXT: jmp .LBB1_5
; DISABLE-NEXT: .LBB1_4: # %if.else
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .LBB1_5: # %if.else
; DISABLE-NEXT: addl %edx, %edx
; DISABLE-NEXT: movl %edx, %eax
; DISABLE-NEXT: .LBB1_5: # %if.end
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .seh_endproc
Expand Down
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