diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 92d00c26bd219..4c2fcd38bd35a 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -43,14 +43,22 @@ class RISCVInstructionSelector : public InstructionSelector { const RISCVRegisterBankInfo &RBI); bool select(MachineInstr &MI) override; + + void setupMF(MachineFunction &MF, GISelKnownBits *KB, + CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI) override { + InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI); + MRI = &MF.getRegInfo(); + } + static const char *getName() { return DEBUG_TYPE; } private: const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const; - bool isRegInGprb(Register Reg, MachineRegisterInfo &MRI) const; - bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const; + bool isRegInGprb(Register Reg) const; + bool isRegInFprb(Register Reg) const; // tblgen-erated 'select' implementation, used as the initial selector for // the patterns that don't require complex C++. @@ -58,31 +66,23 @@ class RISCVInstructionSelector : public InstructionSelector { // A lowering phase that runs before any selection attempts. // Returns true if the instruction was modified. - void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI); + void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB); - bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI); + bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB); // Custom selection methods - bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const; - bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const; + bool selectCopy(MachineInstr &MI) const; + bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB) const; bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const; - bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI, bool IsLocal = true, + bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB, bool IsLocal = true, bool IsExternWeak = false) const; bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const; - bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const; - bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const; + bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB) const; + bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB) const; void emitFence(AtomicOrdering FenceOrdering, SyncScope::ID FenceSSID, MachineIRBuilder &MIB) const; - bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const; - bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const; + bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const; + bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const; ComplexRendererFns selectShiftMask(MachineOperand &Root) const; ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const; @@ -121,6 +121,8 @@ class RISCVInstructionSelector : public InstructionSelector { const RISCVRegisterBankInfo &RBI; const RISCVTargetMachine &TM; + MachineRegisterInfo *MRI = nullptr; + // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel // uses "STI." in the code generated by TableGen. We need to unify the name of // Subtarget variable. @@ -162,16 +164,15 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { return std::nullopt; using namespace llvm::MIPatternMatch; - MachineRegisterInfo &MRI = MF->getRegInfo(); Register RootReg = Root.getReg(); Register ShAmtReg = RootReg; - const LLT ShiftLLT = MRI.getType(RootReg); + const LLT ShiftLLT = MRI->getType(RootReg); unsigned ShiftWidth = ShiftLLT.getSizeInBits(); assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); // Peek through zext. Register ZExtSrcReg; - if (mi_match(ShAmtReg, MRI, m_GZExt(m_Reg(ZExtSrcReg)))) { + if (mi_match(ShAmtReg, *MRI, m_GZExt(m_Reg(ZExtSrcReg)))) { ShAmtReg = ZExtSrcReg; } @@ -191,7 +192,7 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { // // 1. the lowest log2(XLEN) bits of the and mask are all set // 2. the bits of the register being masked are already unset (zero set) - if (mi_match(ShAmtReg, MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { + if (mi_match(ShAmtReg, *MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); if (ShMask.isSubsetOf(AndMask)) { ShAmtReg = AndSrcReg; @@ -206,16 +207,16 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { APInt Imm; Register Reg; - if (mi_match(ShAmtReg, MRI, m_GAdd(m_Reg(Reg), m_ICst(Imm)))) { + if (mi_match(ShAmtReg, *MRI, m_GAdd(m_Reg(Reg), m_ICst(Imm)))) { if (Imm != 0 && Imm.urem(ShiftWidth) == 0) // If we are shifting by X+N where N == 0 mod Size, then just shift by X // to avoid the ADD. ShAmtReg = Reg; - } else if (mi_match(ShAmtReg, MRI, m_GSub(m_ICst(Imm), m_Reg(Reg)))) { + } else if (mi_match(ShAmtReg, *MRI, m_GSub(m_ICst(Imm), m_Reg(Reg)))) { if (Imm != 0 && Imm.urem(ShiftWidth) == 0) { // If we are shifting by N-X where N == 0 mod Size, then just shift by -X // to generate a NEG instead of a SUB of a constant. - ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + ShAmtReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB; return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) @@ -226,7 +227,7 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { if (Imm.urem(ShiftWidth) == ShiftWidth - 1) { // If we are shifting by N-X where N == -1 mod Size, then just shift by ~X // to generate a NOT instead of a SUB of a constant. - ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + ShAmtReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) @@ -243,8 +244,6 @@ InstructionSelector::ComplexRendererFns RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, unsigned ShAmt) const { using namespace llvm::MIPatternMatch; - MachineFunction &MF = *Root.getParent()->getParent()->getParent(); - MachineRegisterInfo &MRI = MF.getRegInfo(); if (!Root.isReg()) return std::nullopt; @@ -255,11 +254,11 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, Register RegY; std::optional LeftShift; // (and (shl y, c2), mask) - if (mi_match(RootReg, MRI, + if (mi_match(RootReg, *MRI, m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask)))) LeftShift = true; // (and (lshr y, c2), mask) - else if (mi_match(RootReg, MRI, + else if (mi_match(RootReg, *MRI, m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask)))) LeftShift = false; @@ -275,7 +274,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, // Given (and (shl y, c2), mask) in which mask has no leading zeros and // c3 trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD. if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt) { - Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) @@ -287,7 +286,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, // Given (and (lshr y, c2), mask) in which mask has c2 leading zeros and // c3 trailing zeros. We can use an SRLI by c2 + c3 followed by a SHXADD. if (!*LeftShift && Leading == C2 && Trailing == ShAmt) { - Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) @@ -301,12 +300,12 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, LeftShift.reset(); // (shl (and y, mask), c2) - if (mi_match(RootReg, MRI, + if (mi_match(RootReg, *MRI, m_GShl(m_OneNonDBGUse(m_GAnd(m_Reg(RegY), m_ICst(Mask))), m_ICst(C2)))) LeftShift = true; // (lshr (and y, mask), c2) - else if (mi_match(RootReg, MRI, + else if (mi_match(RootReg, *MRI, m_GLShr(m_OneNonDBGUse(m_GAnd(m_Reg(RegY), m_ICst(Mask))), m_ICst(C2)))) LeftShift = false; @@ -326,7 +325,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, (Trailing - C2.getLimitedValue()) == ShAmt; if (Cond) { - Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) @@ -343,8 +342,6 @@ InstructionSelector::ComplexRendererFns RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root, unsigned ShAmt) const { using namespace llvm::MIPatternMatch; - MachineFunction &MF = *Root.getParent()->getParent()->getParent(); - MachineRegisterInfo &MRI = MF.getRegInfo(); if (!Root.isReg()) return std::nullopt; @@ -356,7 +353,7 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root, APInt Mask, C2; Register RegX; if (mi_match( - RootReg, MRI, + RootReg, *MRI, m_OneNonDBGUse(m_GAnd(m_OneNonDBGUse(m_GShl(m_Reg(RegX), m_ICst(C2))), m_ICst(Mask))))) { Mask &= maskTrailingZeros(C2.getLimitedValue()); @@ -365,7 +362,7 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root, unsigned Leading = Mask.countl_zero(); unsigned Trailing = Mask.countr_zero(); if (Leading == 32 - ShAmt && C2 == Trailing && Trailing > ShAmt) { - Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) @@ -381,13 +378,10 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root, InstructionSelector::ComplexRendererFns RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const { - MachineFunction &MF = *Root.getParent()->getParent()->getParent(); - MachineRegisterInfo &MRI = MF.getRegInfo(); - if (!Root.isReg()) return std::nullopt; - MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); + MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) { return {{ [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }, @@ -395,11 +389,11 @@ RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const { }}; } - if (isBaseWithConstantOffset(Root, MRI)) { + if (isBaseWithConstantOffset(Root, *MRI)) { MachineOperand &LHS = RootDef->getOperand(1); MachineOperand &RHS = RootDef->getOperand(2); - MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg()); - MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg()); + MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg()); + MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg()); int64_t RHSC = RHSDef->getOperand(1).getCImm()->getSExtValue(); if (isInt<12>(RHSC)) { @@ -441,9 +435,9 @@ static RISCVCC::CondCode getRISCVCCFromICmp(CmpInst::Predicate CC) { } } -static void getOperandsForBranch(Register CondReg, MachineRegisterInfo &MRI, - RISCVCC::CondCode &CC, Register &LHS, - Register &RHS) { +static void getOperandsForBranch(Register CondReg, RISCVCC::CondCode &CC, + Register &LHS, Register &RHS, + MachineRegisterInfo &MRI) { // Try to fold an ICmp. If that fails, use a NE compare with X0. CmpInst::Predicate Pred = CmpInst::BAD_ICMP_PREDICATE; if (!mi_match(CondReg, MRI, m_GICmp(m_Pred(Pred), m_Reg(LHS), m_Reg(RHS)))) { @@ -509,19 +503,18 @@ static void getOperandsForBranch(Register CondReg, MachineRegisterInfo &MRI, bool RISCVInstructionSelector::select(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - MachineRegisterInfo &MRI = MF.getRegInfo(); MachineIRBuilder MIB(MI); - preISelLower(MI, MIB, MRI); + preISelLower(MI, MIB); const unsigned Opc = MI.getOpcode(); if (!MI.isPreISelOpcode() || Opc == TargetOpcode::G_PHI) { if (Opc == TargetOpcode::PHI || Opc == TargetOpcode::G_PHI) { const Register DefReg = MI.getOperand(0).getReg(); - const LLT DefTy = MRI.getType(DefReg); + const LLT DefTy = MRI->getType(DefReg); const RegClassOrRegBank &RegClassOrBank = - MRI.getRegClassOrRegBank(DefReg); + MRI->getRegClassOrRegBank(DefReg); const TargetRegisterClass *DefRC = RegClassOrBank.dyn_cast(); @@ -540,12 +533,12 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { } MI.setDesc(TII.get(TargetOpcode::PHI)); - return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); + return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); } // Certain non-generic instructions also need some special handling. if (MI.isCopy()) - return selectCopy(MI, MRI); + return selectCopy(MI); return true; } @@ -559,7 +552,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { case TargetOpcode::G_INTTOPTR: case TargetOpcode::G_TRUNC: case TargetOpcode::G_FREEZE: - return selectCopy(MI, MRI); + return selectCopy(MI); case TargetOpcode::G_CONSTANT: { Register DstReg = MI.getOperand(0).getReg(); int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue(); @@ -576,9 +569,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { Register DstReg = MI.getOperand(0).getReg(); const APFloat &FPimm = MI.getOperand(1).getFPImm()->getValueAPF(); APInt Imm = FPimm.bitcastToAPInt(); - unsigned Size = MRI.getType(DstReg).getSizeInBits(); + unsigned Size = MRI->getType(DstReg).getSizeInBits(); if (Size == 16 || Size == 32 || (Size == 64 && Subtarget->is64Bit())) { - Register GPRReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register GPRReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB)) return false; @@ -592,8 +585,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { assert(Size == 64 && !Subtarget->is64Bit() && "Unexpected size or subtarget"); // Split into two pieces and build through the stack. - Register GPRRegHigh = MRI.createVirtualRegister(&RISCV::GPRRegClass); - Register GPRRegLow = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register GPRRegHigh = MRI->createVirtualRegister(&RISCV::GPRRegClass); + Register GPRRegLow = MRI->createVirtualRegister(&RISCV::GPRRegClass); if (!materializeImm(GPRRegHigh, Imm.extractBits(32, 32).getSExtValue(), MIB)) return false; @@ -615,8 +608,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return false; } - return selectAddr(MI, MIB, MRI, GV->isDSOLocal(), - GV->hasExternalWeakLinkage()); + return selectAddr(MI, MIB, GV->isDSOLocal(), GV->hasExternalWeakLinkage()); } case TargetOpcode::G_JUMP_TABLE: case TargetOpcode::G_CONSTANT_POOL: @@ -624,7 +616,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { case TargetOpcode::G_BRCOND: { Register LHS, RHS; RISCVCC::CondCode CC; - getOperandsForBranch(MI.getOperand(0).getReg(), MRI, CC, LHS, RHS); + getOperandsForBranch(MI.getOperand(0).getReg(), CC, LHS, RHS, *MRI); auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS}) .addMBB(MI.getOperand(1).getMBB()); @@ -698,9 +690,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); } case TargetOpcode::G_SELECT: - return selectSelect(MI, MIB, MRI); + return selectSelect(MI, MIB); case TargetOpcode::G_FCMP: - return selectFPCompare(MI, MIB, MRI); + return selectFPCompare(MI, MIB); case TargetOpcode::G_FENCE: { AtomicOrdering FenceOrdering = static_cast(MI.getOperand(0).getImm()); @@ -711,18 +703,18 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return true; } case TargetOpcode::G_IMPLICIT_DEF: - return selectImplicitDef(MI, MIB, MRI); + return selectImplicitDef(MI, MIB); case TargetOpcode::G_MERGE_VALUES: - return selectMergeValues(MI, MIB, MRI); + return selectMergeValues(MI, MIB); case TargetOpcode::G_UNMERGE_VALUES: - return selectUnmergeValues(MI, MIB, MRI); + return selectUnmergeValues(MI, MIB); default: return false; } } -bool RISCVInstructionSelector::selectMergeValues( - MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const { +bool RISCVInstructionSelector::selectMergeValues(MachineInstr &MI, + MachineIRBuilder &MIB) const { assert(MI.getOpcode() == TargetOpcode::G_MERGE_VALUES); // Build a F64 Pair from operands @@ -731,14 +723,14 @@ bool RISCVInstructionSelector::selectMergeValues( Register Dst = MI.getOperand(0).getReg(); Register Lo = MI.getOperand(1).getReg(); Register Hi = MI.getOperand(2).getReg(); - if (!isRegInFprb(Dst, MRI) || !isRegInGprb(Lo, MRI) || !isRegInGprb(Hi, MRI)) + if (!isRegInFprb(Dst) || !isRegInGprb(Lo) || !isRegInGprb(Hi)) return false; MI.setDesc(TII.get(RISCV::BuildPairF64Pseudo)); return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); } bool RISCVInstructionSelector::selectUnmergeValues( - MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const { + MachineInstr &MI, MachineIRBuilder &MIB) const { assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); // Split F64 Src into two s32 parts @@ -747,44 +739,42 @@ bool RISCVInstructionSelector::selectUnmergeValues( Register Src = MI.getOperand(2).getReg(); Register Lo = MI.getOperand(0).getReg(); Register Hi = MI.getOperand(1).getReg(); - if (!isRegInFprb(Src, MRI) || !isRegInGprb(Lo, MRI) || !isRegInGprb(Hi, MRI)) + if (!isRegInFprb(Src) || !isRegInGprb(Lo) || !isRegInGprb(Hi)) return false; MI.setDesc(TII.get(RISCV::SplitF64Pseudo)); return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); } bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op, - MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) { + MachineIRBuilder &MIB) { Register PtrReg = Op.getReg(); - assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!"); + assert(MRI->getType(PtrReg).isPointer() && "Operand is not a pointer!"); const LLT sXLen = LLT::scalar(STI.getXLen()); auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg); - MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID)); + MRI->setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID)); Op.setReg(PtrToInt.getReg(0)); return select(*PtrToInt); } void RISCVInstructionSelector::preISelLower(MachineInstr &MI, - MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) { + MachineIRBuilder &MIB) { switch (MI.getOpcode()) { case TargetOpcode::G_PTR_ADD: { Register DstReg = MI.getOperand(0).getReg(); const LLT sXLen = LLT::scalar(STI.getXLen()); - replacePtrWithInt(MI.getOperand(1), MIB, MRI); + replacePtrWithInt(MI.getOperand(1), MIB); MI.setDesc(TII.get(TargetOpcode::G_ADD)); - MRI.setType(DstReg, sXLen); + MRI->setType(DstReg, sXLen); break; } case TargetOpcode::G_PTRMASK: { Register DstReg = MI.getOperand(0).getReg(); const LLT sXLen = LLT::scalar(STI.getXLen()); - replacePtrWithInt(MI.getOperand(1), MIB, MRI); + replacePtrWithInt(MI.getOperand(1), MIB); MI.setDesc(TII.get(TargetOpcode::G_AND)); - MRI.setType(DstReg, sXLen); + MRI->setType(DstReg, sXLen); } } } @@ -876,32 +866,29 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank( return nullptr; } -bool RISCVInstructionSelector::isRegInGprb(Register Reg, - MachineRegisterInfo &MRI) const { - return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::GPRBRegBankID; +bool RISCVInstructionSelector::isRegInGprb(Register Reg) const { + return RBI.getRegBank(Reg, *MRI, TRI)->getID() == RISCV::GPRBRegBankID; } -bool RISCVInstructionSelector::isRegInFprb(Register Reg, - MachineRegisterInfo &MRI) const { - return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::FPRBRegBankID; +bool RISCVInstructionSelector::isRegInFprb(Register Reg) const { + return RBI.getRegBank(Reg, *MRI, TRI)->getID() == RISCV::FPRBRegBankID; } -bool RISCVInstructionSelector::selectCopy(MachineInstr &MI, - MachineRegisterInfo &MRI) const { +bool RISCVInstructionSelector::selectCopy(MachineInstr &MI) const { Register DstReg = MI.getOperand(0).getReg(); if (DstReg.isPhysical()) return true; const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( - MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); + MRI->getType(DstReg), *RBI.getRegBank(DstReg, *MRI, TRI)); assert(DstRC && "Register class not available for LLT, register bank combination"); // No need to constrain SrcReg. It will get constrained when // we hit another of its uses or its defs. // Copies do not have constraints. - if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode()) << " operand\n"); return false; @@ -911,18 +898,18 @@ bool RISCVInstructionSelector::selectCopy(MachineInstr &MI, return true; } -bool RISCVInstructionSelector::selectImplicitDef( - MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const { +bool RISCVInstructionSelector::selectImplicitDef(MachineInstr &MI, + MachineIRBuilder &MIB) const { assert(MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF); const Register DstReg = MI.getOperand(0).getReg(); const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( - MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); + MRI->getType(DstReg), *RBI.getRegBank(DstReg, *MRI, TRI)); assert(DstRC && "Register class not available for LLT, register bank combination"); - if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode()) << " operand\n"); } @@ -932,11 +919,9 @@ bool RISCVInstructionSelector::selectImplicitDef( bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm, MachineIRBuilder &MIB) const { - MachineRegisterInfo &MRI = *MIB.getMRI(); - if (Imm == 0) { MIB.buildCopy(DstReg, Register(RISCV::X0)); - RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, MRI); + RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, *MRI); return true; } @@ -946,7 +931,7 @@ bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm, for (unsigned i = 0; i < NumInsts; i++) { Register TmpReg = i < NumInsts - 1 - ? MRI.createVirtualRegister(&RISCV::GPRRegClass) + ? MRI->createVirtualRegister(&RISCV::GPRRegClass) : DstReg; const RISCVMatInt::Inst &I = Seq[i]; MachineInstr *Result; @@ -981,9 +966,7 @@ bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm, } bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, - MachineIRBuilder &MIB, - MachineRegisterInfo &MRI, - bool IsLocal, + MachineIRBuilder &MIB, bool IsLocal, bool IsExternWeak) const { assert((MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE || MI.getOpcode() == TargetOpcode::G_JUMP_TABLE || @@ -993,7 +976,7 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, const MachineOperand &DispMO = MI.getOperand(1); Register DefReg = MI.getOperand(0).getReg(); - const LLT DefTy = MRI.getType(DefReg); + const LLT DefTy = MRI->getType(DefReg); // When HWASAN is used and tagging of global variables is enabled // they should be accessed via the GOT, since the tagged address of a global @@ -1040,7 +1023,7 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, // Must lie within a single 2 GiB address range and must lie between // absolute addresses -2 GiB and +2 GiB. This generates the pattern (addi // (lui %hi(sym)) %lo(sym)). - Register AddrHiDest = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register AddrHiDest = MRI->createVirtualRegister(&RISCV::GPRRegClass); MachineInstr *AddrHi = MIB.buildInstr(RISCV::LUI, {AddrHiDest}, {}) .addDisp(DispMO, 0, RISCVII::MO_HI); @@ -1120,19 +1103,18 @@ bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI, } bool RISCVInstructionSelector::selectSelect(MachineInstr &MI, - MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const { + MachineIRBuilder &MIB) const { auto &SelectMI = cast(MI); Register LHS, RHS; RISCVCC::CondCode CC; - getOperandsForBranch(SelectMI.getCondReg(), MRI, CC, LHS, RHS); + getOperandsForBranch(SelectMI.getCondReg(), CC, LHS, RHS, *MRI); Register DstReg = SelectMI.getReg(0); unsigned Opc = RISCV::Select_GPR_Using_CC_GPR; - if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) { - unsigned Size = MRI.getType(DstReg).getSizeInBits(); + if (RBI.getRegBank(DstReg, *MRI, TRI)->getID() == RISCV::FPRBRegBankID) { + unsigned Size = MRI->getType(DstReg).getSizeInBits(); Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR : RISCV::Select_FPR64_Using_CC_GPR; } @@ -1201,8 +1183,7 @@ static bool legalizeFCmpPredicate(Register &LHS, Register &RHS, // the result in DstReg. // FIXME: Maybe we should expand this earlier. bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, - MachineIRBuilder &MIB, - MachineRegisterInfo &MRI) const { + MachineIRBuilder &MIB) const { auto &CmpMI = cast(MI); CmpInst::Predicate Pred = CmpMI.getCond(); @@ -1210,7 +1191,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, Register LHS = CmpMI.getLHSReg(); Register RHS = CmpMI.getRHSReg(); - unsigned Size = MRI.getType(LHS).getSizeInBits(); + unsigned Size = MRI->getType(LHS).getSizeInBits(); assert((Size == 16 || Size == 32 || Size == 64) && "Unexpected size"); Register TmpReg = DstReg; @@ -1219,7 +1200,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, // First try swapping operands or inverting. if (legalizeFCmpPredicate(LHS, RHS, Pred, NeedInvert)) { if (NeedInvert) - TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS}); if (!Cmp.constrainAllUses(TII, TRI, RBI)) return false; @@ -1235,7 +1216,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, if (!Cmp2.constrainAllUses(TII, TRI, RBI)) return false; if (NeedInvert) - TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto Or = MIB.buildInstr(RISCV::OR, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)}); if (!Or.constrainAllUses(TII, TRI, RBI)) @@ -1253,7 +1234,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, if (!Cmp2.constrainAllUses(TII, TRI, RBI)) return false; if (NeedInvert) - TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto And = MIB.buildInstr(RISCV::AND, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)}); if (!And.constrainAllUses(TII, TRI, RBI))