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[HLSL] implement elementwise firstbithigh hlsl builtin#111082

Merged

spall merged 12 commits intollvm:mainllvm/llvm-project:mainfrom

spall:issue-99115spall/llvm-project:issue-99115Copy head branch name to clipboard

Nov 6, 2024

Conversation Commits12 (12)Checks Files changed

Merged

[HLSL] implement elementwise firstbithigh hlsl builtin#111082
spall merged 12 commits intollvm:mainfrom
spall:issue-99115

Commits

Commits on Nov 5, 2024

implement firstbithigh hlsl builtin
spall
committed
make clang format happy
spall
committed
address PR comments
spall
committed
update firstbithigh to the correct behavior. both dxil and spirv support 16, 32, and 64 bit now.
spall
committed
make clang format happy
spall
committed
switch to unaryBits
spall
committed
address pr comments
spall
committed
remove use of vectors of length 1 in firstbithigh64 code
spall
committed
address pr comments
spall
committed
cast to unsigned
spall
committed
address comment
spall
committed
fix clang format error
spall
committed

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