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[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes. #111774

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Oct 14, 2024
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[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes. #111774

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match select icmp
c8ef Oct 10, 2024
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update test
c8ef Oct 10, 2024
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c8ef Oct 10, 2024
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98 changes: 98 additions & 0 deletions llvm/include/llvm/CodeGen/SDPatternMatch.h
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Expand Up @@ -542,6 +542,80 @@ struct BinaryOpc_match {
}
};

template <typename LHS_P, typename RHS_P, typename Pred_t,
bool Commutable = false, bool ExcludeChain = false>
struct MaxMin_match {
using PredType = Pred_t;
LHS_P LHS;
RHS_P RHS;

MaxMin_match(const LHS_P &L, const RHS_P &R) : LHS(L), RHS(R) {}

template <typename MatchContext>
bool match(const MatchContext &Ctx, SDValue N) {
if (sd_context_match(N, Ctx, m_Opc(ISD::SELECT))) {
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@RKSimon RKSimon Oct 12, 2024

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What about ISD::VSELECT?

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@c8ef c8ef Oct 12, 2024

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Done.

EffectiveOperands<ExcludeChain> EO_SELECT(N, Ctx);
assert(EO_SELECT.Size == 3);
SDValue Cond = N->getOperand(EO_SELECT.FirstIndex);
SDValue TrueValue = N->getOperand(EO_SELECT.FirstIndex + 1);
SDValue FalseValue = N->getOperand(EO_SELECT.FirstIndex + 2);

if (sd_context_match(Cond, Ctx, m_Opc(ISD::SETCC))) {
EffectiveOperands<ExcludeChain> EO_SETCC(Cond, Ctx);
assert(EO_SETCC.Size == 3);
SDValue L = Cond->getOperand(EO_SETCC.FirstIndex);
SDValue R = Cond->getOperand(EO_SETCC.FirstIndex + 1);
CondCodeSDNode *CondNode =
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@RKSimon RKSimon Oct 12, 2024

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(style) auto *CondNode =

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@c8ef c8ef Oct 12, 2024

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Done.

cast<CondCodeSDNode>(Cond->getOperand(EO_SETCC.FirstIndex + 2));

if ((TrueValue != L || FalseValue != R) &&
(TrueValue != R || FalseValue != L)) {
return false;
}

ISD::CondCode Cond =
TrueValue == L ? CondNode->get()
: getSetCCInverse(CondNode->get(), L.getValueType());
if (!Pred_t::match(Cond)) {
return false;
}
return (LHS.match(Ctx, L) && RHS.match(Ctx, R)) ||
(Commutable && LHS.match(Ctx, R) && RHS.match(Ctx, L));
}
}

return false;
}
};

// Helper class for identifying signed max predicates.
struct smax_pred_ty {
static bool match(ISD::CondCode Cond) {
return Cond == ISD::CondCode::SETGT || Cond == ISD::CondCode::SETGE;
}
};

// Helper class for identifying unsigned max predicates.
struct umax_pred_ty {
static bool match(ISD::CondCode Cond) {
return Cond == ISD::CondCode::SETUGT || Cond == ISD::CondCode::SETUGE;
}
};

// Helper class for identifying signed min predicates.
struct smin_pred_ty {
static bool match(ISD::CondCode Cond) {
return Cond == ISD::CondCode::SETLT || Cond == ISD::CondCode::SETLE;
}
};

// Helper class for identifying unsigned min predicates.
struct umin_pred_ty {
static bool match(ISD::CondCode Cond) {
return Cond == ISD::CondCode::SETULT || Cond == ISD::CondCode::SETULE;
}
};

template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS> m_BinOp(unsigned Opc, const LHS &L,
const RHS &R) {
Expand Down Expand Up @@ -613,21 +687,45 @@ inline BinaryOpc_match<LHS, RHS, true> m_SMin(const LHS &L, const RHS &R) {
return BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R);
}

template <typename LHS, typename RHS>
inline auto m_SMinLike(const LHS &L, const RHS &R) {
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R),
MaxMin_match<LHS, RHS, smin_pred_ty, true>(L, R));
}

template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS, true> m_SMax(const LHS &L, const RHS &R) {
return BinaryOpc_match<LHS, RHS, true>(ISD::SMAX, L, R);
}

template <typename LHS, typename RHS>
inline auto m_SMaxLike(const LHS &L, const RHS &R) {
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::SMAX, L, R),
MaxMin_match<LHS, RHS, smax_pred_ty, true>(L, R));
}

template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS, true> m_UMin(const LHS &L, const RHS &R) {
return BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R);
}

template <typename LHS, typename RHS>
inline auto m_UMinLike(const LHS &L, const RHS &R) {
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R),
MaxMin_match<LHS, RHS, umin_pred_ty, true>(L, R));
}

template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS, true> m_UMax(const LHS &L, const RHS &R) {
return BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R);
}

template <typename LHS, typename RHS>
inline auto m_UMaxLike(const LHS &L, const RHS &R) {
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R),
MaxMin_match<LHS, RHS, umax_pred_ty, true>(L, R));
}

template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS> m_UDiv(const LHS &L, const RHS &R) {
return BinaryOpc_match<LHS, RHS>(ISD::UDIV, L, R);
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -4190,26 +4190,26 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {

// smax(a,b) - smin(a,b) --> abds(a,b)
if ((!LegalOperations || hasOperation(ISD::ABDS, VT)) &&
sd_match(N0, m_SMax(m_Value(A), m_Value(B))) &&
sd_match(N1, m_SMin(m_Specific(A), m_Specific(B))))
sd_match(N0, m_SMaxLike(m_Value(A), m_Value(B))) &&
sd_match(N1, m_SMinLike(m_Specific(A), m_Specific(B))))
return DAG.getNode(ISD::ABDS, DL, VT, A, B);

// smin(a,b) - smax(a,b) --> neg(abds(a,b))
if (hasOperation(ISD::ABDS, VT) &&
sd_match(N0, m_SMin(m_Value(A), m_Value(B))) &&
sd_match(N1, m_SMax(m_Specific(A), m_Specific(B))))
sd_match(N0, m_SMinLike(m_Value(A), m_Value(B))) &&
sd_match(N1, m_SMaxLike(m_Specific(A), m_Specific(B))))
return DAG.getNegative(DAG.getNode(ISD::ABDS, DL, VT, A, B), DL, VT);

// umax(a,b) - umin(a,b) --> abdu(a,b)
if ((!LegalOperations || hasOperation(ISD::ABDU, VT)) &&
sd_match(N0, m_UMax(m_Value(A), m_Value(B))) &&
sd_match(N1, m_UMin(m_Specific(A), m_Specific(B))))
sd_match(N0, m_UMaxLike(m_Value(A), m_Value(B))) &&
sd_match(N1, m_UMinLike(m_Specific(A), m_Specific(B))))
return DAG.getNode(ISD::ABDU, DL, VT, A, B);

// umin(a,b) - umax(a,b) --> neg(abdu(a,b))
if (hasOperation(ISD::ABDU, VT) &&
sd_match(N0, m_UMin(m_Value(A), m_Value(B))) &&
sd_match(N1, m_UMax(m_Specific(A), m_Specific(B))))
sd_match(N0, m_UMinLike(m_Value(A), m_Value(B))) &&
sd_match(N1, m_UMaxLike(m_Specific(A), m_Specific(B))))
return DAG.getNegative(DAG.getNode(ISD::ABDU, DL, VT, A, B), DL, VT);

return SDValue();
Expand Down
43 changes: 19 additions & 24 deletions llvm/test/CodeGen/AArch64/abds.ll
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Expand Up @@ -547,10 +547,9 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_select_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: cmp w8, w1, sxtb
; CHECK-NEXT: csel w8, w0, w1, lt
; CHECK-NEXT: csel w9, w1, w0, lt
; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp slt i8 %a, %b
%ab = select i1 %cmp, i8 %a, i8 %b
Expand All @@ -563,10 +562,9 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_select_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmp w8, w1, sxth
; CHECK-NEXT: csel w8, w0, w1, le
; CHECK-NEXT: csel w9, w1, w0, le
; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sle i16 %a, %b
%ab = select i1 %cmp, i16 %a, i16 %b
Expand All @@ -578,10 +576,9 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_select_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: csel w8, w0, w1, gt
; CHECK-NEXT: csel w9, w1, w0, gt
; CHECK-NEXT: sub w0, w8, w9
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %a, %b
%ab = select i1 %cmp, i32 %a, i32 %b
Expand All @@ -593,10 +590,9 @@ define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_select_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: csel x8, x0, x1, ge
; CHECK-NEXT: csel x9, x1, x0, ge
; CHECK-NEXT: sub x0, x8, x9
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%cmp = icmp sge i64 %a, %b
%ab = select i1 %cmp, i64 %a, i64 %b
Expand All @@ -608,14 +604,13 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_select_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: sbcs xzr, x1, x3
; CHECK-NEXT: csel x8, x0, x2, lt
; CHECK-NEXT: csel x9, x2, x0, lt
; CHECK-NEXT: csel x10, x1, x3, lt
; CHECK-NEXT: csel x11, x3, x1, lt
; CHECK-NEXT: subs x0, x9, x8
; CHECK-NEXT: sbc x1, x11, x10
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
; CHECK-NEXT: sbc x11, x3, x1
; CHECK-NEXT: sbcs xzr, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
%cmp = icmp slt i128 %a, %b
%ab = select i1 %cmp, i128 %a, i128 %b
Expand Down
44 changes: 20 additions & 24 deletions llvm/test/CodeGen/AArch64/abdu.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -408,10 +408,9 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_select_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmp w8, w1, uxtb
; CHECK-NEXT: csel w8, w0, w1, lo
; CHECK-NEXT: csel w9, w1, w0, lo
; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ult i8 %a, %b
%ab = select i1 %cmp, i8 %a, i8 %b
Expand All @@ -424,10 +423,9 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_select_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: cmp w8, w1, uxth
; CHECK-NEXT: csel w8, w0, w1, ls
; CHECK-NEXT: csel w9, w1, w0, ls
; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ule i16 %a, %b
%ab = select i1 %cmp, i16 %a, i16 %b
Expand All @@ -439,10 +437,9 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_select_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: csel w8, w0, w1, hi
; CHECK-NEXT: csel w9, w1, w0, hi
; CHECK-NEXT: sub w0, w8, w9
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%cmp = icmp ugt i32 %a, %b
%ab = select i1 %cmp, i32 %a, i32 %b
Expand All @@ -454,10 +451,9 @@ define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_select_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: csel x8, x0, x1, hs
; CHECK-NEXT: csel x9, x1, x0, hs
; CHECK-NEXT: sub x0, x8, x9
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%cmp = icmp uge i64 %a, %b
%ab = select i1 %cmp, i64 %a, i64 %b
Expand All @@ -469,14 +465,14 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_select_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: sbcs xzr, x1, x3
; CHECK-NEXT: csel x8, x0, x2, lo
; CHECK-NEXT: csel x9, x2, x0, lo
; CHECK-NEXT: csel x10, x1, x3, lo
; CHECK-NEXT: csel x11, x3, x1, lo
; CHECK-NEXT: subs x0, x9, x8
; CHECK-NEXT: sbc x1, x11, x10
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbcs x9, x1, x3
; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: sbfx x10, x10, #0, #1
; CHECK-NEXT: eor x8, x8, x10
; CHECK-NEXT: eor x9, x9, x10
; CHECK-NEXT: subs x0, x8, x10
; CHECK-NEXT: sbc x1, x9, x10
; CHECK-NEXT: ret
%cmp = icmp ult i128 %a, %b
%ab = select i1 %cmp, i128 %a, i128 %b
Expand Down
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