From 200c33064f439ada0d8910af98602b1e08ce2283 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 14 Oct 2024 19:43:41 +0100 Subject: [PATCH 1/3] Precommit test --- llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vl-opt.mir diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir new file mode 100644 index 0000000000000..e72f454746880 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -0,0 +1,18 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vnsrl_wv_user +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vnsrl_wv_user + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ +... From 7c4648249388e740193a6748a62f0707bea66b1d Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 14 Oct 2024 19:48:28 +0100 Subject: [PATCH 2/3] [RISCV][VLOPT] Fix passthru check in getOperandInfo If a pseudo has a passthru, I believe the first source operand will be the second operand, not the first. I've added an MIR test which should show how we're reading the wrong SEW, but in order to be able to use -run-pass=riscv-vl-optimizer I needed to initialize the pass in RISCVTargetMachine.cpp. --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 + llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 4 ++-- llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index c48470ab707f1..089dc6c529193 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -128,6 +128,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVPreRAExpandPseudoPass(*PR); initializeRISCVExpandPseudoPass(*PR); initializeRISCVVectorPeepholePass(*PR); + initializeRISCVVLOptimizerPass(*PR); initializeRISCVInsertVSETVLIPass(*PR); initializeRISCVInsertReadWriteCSRPass(*PR); initializeRISCVInsertWriteVXRMPass(*PR); diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index eb1f4df4ff726..d4d66c4e1cec5 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -431,7 +431,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI, case RISCV::VWMACCSU_VV: case RISCV::VWMACCSU_VX: case RISCV::VWMACCUS_VX: { - bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2; + bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1; bool TwoTimes = IsMODef || IsOp1; unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW; RISCVII::VLMUL EMUL = @@ -467,7 +467,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI, case RISCV::VNCLIP_WI: case RISCV::VNCLIP_WV: case RISCV::VNCLIP_WX: { - bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2; + bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1; bool TwoTimes = IsOp1; unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW; RISCVII::VLMUL EMUL = diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir index e72f454746880..59a472c73a462 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -10,7 +10,7 @@ body: | ; CHECK: liveins: $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ %vl:gprnox0 = COPY $x1 %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ From 676cc660a5fb3d8369ef37f437c8fb6f1f34094c Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 14 Oct 2024 20:52:14 +0100 Subject: [PATCH 3/3] Update another test --- llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll | 48 ++++++++++++------- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll index 6e604d200a627..1a01a9bf77cff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll @@ -40,13 +40,20 @@ declare @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16( iXLen); define @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16( %a, %b, iXLen %2, %3, %4, %z) nounwind { -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-NEXT: vwadd.vv v10, v8, v9 -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: vnsrl.wv v8, v10, v12 -; CHECK-NEXT: ret +; NOVLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16: +; NOVLOPT: # %bb.0: # %entry +; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; NOVLOPT-NEXT: vwadd.vv v10, v8, v9 +; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; NOVLOPT-NEXT: vnsrl.wv v8, v10, v12 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16: +; VLOPT: # %bb.0: # %entry +; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; VLOPT-NEXT: vwadd.vv v10, v8, v9 +; VLOPT-NEXT: vnsrl.wv v8, v10, v12 +; VLOPT-NEXT: ret entry: %c = sext %a to %d = sext %b to @@ -67,14 +74,22 @@ declare @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16( iXLen, iXLen); define @vnclip( %a, %b, iXLen %2, %3, %4, %z) nounwind { -; CHECK-LABEL: vnclip: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-NEXT: vwadd.vv v10, v8, v9 -; CHECK-NEXT: csrwi vxrm, 0 -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: vnclip.wv v8, v10, v12 -; CHECK-NEXT: ret +; NOVLOPT-LABEL: vnclip: +; NOVLOPT: # %bb.0: # %entry +; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; NOVLOPT-NEXT: vwadd.vv v10, v8, v9 +; NOVLOPT-NEXT: csrwi vxrm, 0 +; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; NOVLOPT-NEXT: vnclip.wv v8, v10, v12 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vnclip: +; VLOPT: # %bb.0: # %entry +; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; VLOPT-NEXT: vwadd.vv v10, v8, v9 +; VLOPT-NEXT: csrwi vxrm, 0 +; VLOPT-NEXT: vnclip.wv v8, v10, v12 +; VLOPT-NEXT: ret entry: %c = sext %a to %d = sext %b to @@ -88,6 +103,3 @@ entry: ret %x } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; NOVLOPT: {{.*}} -; VLOPT: {{.*}}