diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 7357aa3c1f0d5..9df9aa03097aa 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -131,6 +131,33 @@ defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>; } +let Predicates = [HasSME2p2] in { + defm SMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b0, "smop4a">; + defm SMOP4S : sme_quarter_outer_product_i8_i32<0b0, 0b0, 0b1, "smop4s">; + defm SUMOP4A : sme_quarter_outer_product_i8_i32<0b0, 0b1, 0b0, "sumop4a">; + defm SUMOP4S : sme_quarter_outer_product_i8_i32<0b0, 0b1, 0b1, "sumop4s">; + defm USMOP4A : sme_quarter_outer_product_i8_i32<0b1, 0b0, 0b0, "usmop4a">; + defm USMOP4S : sme_quarter_outer_product_i8_i32<0b1, 0b0, 0b1, "usmop4s">; + defm UMOP4A : sme_quarter_outer_product_i8_i32<0b1, 0b1, 0b0, "umop4a">; + defm UMOP4S : sme_quarter_outer_product_i8_i32<0b1, 0b1, 0b1, "umop4s">; + + defm SMOP4A : sme_quarter_outer_product_i16_i32<0b0, 0b0, "smop4a">; + defm SMOP4S : sme_quarter_outer_product_i16_i32<0b0, 0b1, "smop4s">; + defm UMOP4A : sme_quarter_outer_product_i16_i32<0b1, 0b0, "umop4a">; + defm UMOP4S : sme_quarter_outer_product_i16_i32<0b1, 0b1, "umop4s">; +} + +let Predicates = [HasSME2p2, HasSMEI16I64] in { + defm SMOP4A : sme_quarter_outer_product_i64<0b0, 0b0, 0b0, "smop4a">; + defm SMOP4S : sme_quarter_outer_product_i64<0b0, 0b0, 0b1, "smop4s">; + defm SUMOP4A : sme_quarter_outer_product_i64<0b0, 0b1, 0b0, "sumop4a">; + defm SUMOP4S : sme_quarter_outer_product_i64<0b0, 0b1, 0b1, "sumop4s">; + defm UMOP4A : sme_quarter_outer_product_i64<0b1, 0b1, 0b0, "umop4a">; + defm UMOP4S : sme_quarter_outer_product_i64<0b1, 0b1, 0b1, "umop4s">; + defm USMOP4A : sme_quarter_outer_product_i64<0b1, 0b0, 0b0, "usmop4a">; + defm USMOP4S : sme_quarter_outer_product_i64<0b1, 0b0, 0b1, "usmop4s">; +} + let Predicates = [HasSME] in { //===----------------------------------------------------------------------===// // Loads and stores diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 867901ac5d903..3a02778e92aea 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -433,6 +433,116 @@ multiclass sme_f16_outer_product opc, string mnemonic, SDPatternOperator def : SME_ZA_Tile_TwoPred_TwoVec_Pat; } +class sme_quarter_outer_product_i64 zn_u_pair, bits<2> zm_u_pair, bit subtr, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic> + : I<(outs TileOp64:$ZAda), + (ins TileOp64:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, + Sched<[]> { + bits<3> ZAda; + bits<3> Zn; + bits<3> Zm; + let Inst{31-25} = 0b1010000; + let Inst{24} = zn_u_pair{1}; // u0 + let Inst{23-22} = 0b11; + let Inst{21} = zm_u_pair{1}; // u1 + let Inst{20} = zm_u_pair{0}; // M + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = zn_u_pair{0}; // N + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = subtr; + let Inst{3} = 0b1; + let Inst{2-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +class sme_quarter_outer_product_i8_i32 zn_u_pair, bits<2> zm_u_pair, bit subtr, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic> + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, + Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + let Inst{31-25} = 0b1000000; + let Inst{24} = zn_u_pair{1}; // u0 + let Inst{23-22} = 0b00; + let Inst{21} = zm_u_pair{1}; // u1 + let Inst{20} = zm_u_pair{0}; // M + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0100000; + let Inst{9} = zn_u_pair{0}; // N + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = subtr; + let Inst{3-2} = 0b00; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +class sme_quarter_outer_product_i16_i32 + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, + Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + let Inst{31-25} = 0b1000000; + let Inst{24} = u0; + let Inst{23-21} = 0b000; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0100000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = subtr; + let Inst{3-2} = 0b10; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme_quarter_outer_product_i8_i32{ + def _MZZ_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 0}, {zm_u, 0}, subtr, + ZPR8Mul2_Lo, ZPR8Mul2_Hi, mnemonic>; + def _M2ZZ_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 1}, {zm_u, 0}, subtr, + ZZ_b_mul_r_Lo, ZPR8Mul2_Hi, mnemonic>; + def _MZ2Z_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 0}, {zm_u, 1}, subtr, + ZPR8Mul2_Lo, ZZ_b_mul_r_Hi, mnemonic>; + def _M2Z2Z_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 1}, {zm_u, 1}, subtr, + ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi, mnemonic>; +} + +multiclass sme_quarter_outer_product_i16_i32{ + def _MZZ_HToS : sme_quarter_outer_product_i16_i32; + def _M2ZZ_HToS : sme_quarter_outer_product_i16_i32; + def _MZ2Z_HToS : sme_quarter_outer_product_i16_i32; + def _M2Z2Z_HToS : sme_quarter_outer_product_i16_i32; +} + +multiclass sme_quarter_outer_product_i64{ + def _MZZ_HtoD : sme_quarter_outer_product_i64<{zn_u, 0}, {zm_u, 0}, subtr, + ZPR16Mul2_Lo, ZPR16Mul2_Hi, mnemonic>; + def _M2ZZ_HtoD : sme_quarter_outer_product_i64<{zn_u, 1}, {zm_u, 0}, subtr, + ZZ_h_mul_r_Lo, ZPR16Mul2_Hi, mnemonic>; + def _MZ2Z_HtoD : sme_quarter_outer_product_i64<{zn_u, 0}, {zm_u, 1}, subtr, + ZPR16Mul2_Lo, ZZ_h_mul_r_Hi, mnemonic>; + def _M2Z2Z_HtoD : sme_quarter_outer_product_i64<{zn_u, 1}, {zm_u, 1}, subtr, + ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi, mnemonic>; +} + //===----------------------------------------------------------------------===// // SME Add Vector to Tile //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AArch64/SME2p2/smop4a-16to32.s b/llvm/test/MC/AArch64/SME2p2/smop4a-16to32.s new file mode 100644 index 0000000000000..fe4de7307ec50 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4a-16to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4a za0.s, z0.h, z16.h // 10000000-00000000-10000000-00001000 +// CHECK-INST: smop4a za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x80,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008008 + +smop4a za3.s, z12.h, z24.h // 10000000-00001000-10000001-10001011 +// CHECK-INST: smop4a za3.s, z12.h, z24.h +// CHECK-ENCODING: [0x8b,0x81,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8008818b + +smop4a za3.s, z14.h, z30.h // 10000000-00001110-10000001-11001011 +// CHECK-INST: smop4a za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xcb,0x81,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e81cb + +smop4a za0.s, z0.h, {z16.h-z17.h} // 10000000-00010000-10000000-00001000 +// CHECK-INST: smop4a za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x80,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108008 + +smop4a za3.s, z12.h, {z24.h-z25.h} // 10000000-00011000-10000001-10001011 +// CHECK-INST: smop4a za3.s, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x8b,0x81,0x18,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8018818b + +smop4a za3.s, z14.h, {z30.h-z31.h} // 10000000-00011110-10000001-11001011 +// CHECK-INST: smop4a za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcb,0x81,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e81cb + +smop4a za0.s, {z0.h-z1.h}, z16.h // 10000000-00000000-10000010-00001000 +// CHECK-INST: smop4a za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x82,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008208 + +smop4a za3.s, {z12.h-z13.h}, z24.h // 10000000-00001000-10000011-10001011 +// CHECK-INST: smop4a za3.s, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x8b,0x83,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8008838b + +smop4a za3.s, {z14.h-z15.h}, z30.h // 10000000-00001110-10000011-11001011 +// CHECK-INST: smop4a za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcb,0x83,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e83cb + +smop4a za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000000-00010000-10000010-00001000 +// CHECK-INST: smop4a za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x82,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108208 + +smop4a za3.s, {z12.h-z13.h}, {z24.h-z25.h} // 10000000-00011000-10000011-10001011 +// CHECK-INST: smop4a za3.s, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x8b,0x83,0x18,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8018838b + +smop4a za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000000-00011110-10000011-11001011 +// CHECK-INST: smop4a za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcb,0x83,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e83cb diff --git a/llvm/test/MC/AArch64/SME2p2/smop4a-64.s b/llvm/test/MC/AArch64/SME2p2/smop4a-64.s new file mode 100644 index 0000000000000..be9b6aaa47ecc --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4a-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4a za0.d, z0.h, z16.h // 10100000-11000000-00000000-00001000 +// CHECK-INST: smop4a za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0xc0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c00008 + +smop4a za5.d, z10.h, z20.h // 10100000-11000100-00000001-01001101 +// CHECK-INST: smop4a za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x4d,0x01,0xc4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c4014d + +smop4a za7.d, z14.h, z30.h // 10100000-11001110-00000001-11001111 +// CHECK-INST: smop4a za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xcf,0x01,0xce,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ce01cf + +smop4a za0.d, z0.h, {z16.h-z17.h} // 10100000-11010000-00000000-00001000 +// CHECK-INST: smop4a za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0xd0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d00008 + +smop4a za5.d, z10.h, {z20.h-z21.h} // 10100000-11010100-00000001-01001101 +// CHECK-INST: smop4a za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x01,0xd4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d4014d + +smop4a za7.d, z14.h, {z30.h-z31.h} // 10100000-11011110-00000001-11001111 +// CHECK-INST: smop4a za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x01,0xde,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0de01cf + +smop4a za0.d, {z0.h-z1.h}, z16.h // 10100000-11000000-00000010-00001000 +// CHECK-INST: smop4a za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0xc0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c00208 + +smop4a za5.d, {z10.h-z11.h}, z20.h // 10100000-11000100-00000011-01001101 +// CHECK-INST: smop4a za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x4d,0x03,0xc4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c4034d + +smop4a za7.d, {z14.h-z15.h}, z30.h // 10100000-11001110-00000011-11001111 +// CHECK-INST: smop4a za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcf,0x03,0xce,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ce03cf + +smop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100000-11010000-00000010-00001000 +// CHECK-INST: smop4a za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0xd0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d00208 + +smop4a za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100000-11010100-00000011-01001101 +// CHECK-INST: smop4a za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x03,0xd4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d4034d + +smop4a za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100000-11011110-00000011-11001111 +// CHECK-INST: smop4a za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x03,0xde,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0de03cf diff --git a/llvm/test/MC/AArch64/SME2p2/smop4a-8to32.s b/llvm/test/MC/AArch64/SME2p2/smop4a-8to32.s new file mode 100644 index 0000000000000..0615c8fc690d8 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4a-8to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4a za0.s, z0.b, z16.b // 10000000-00000000-10000000-00000000 +// CHECK-INST: smop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x80,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008000 + +smop4a za1.s, z10.b, z20.b // 10000000-00000100-10000001-01000001 +// CHECK-INST: smop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x81,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80048141 + +smop4a za3.s, z14.b, z30.b // 10000000-00001110-10000001-11000011 +// CHECK-INST: smop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x81,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e81c3 + +smop4a za0.s, z0.b, {z16.b-z17.b} // 10000000-00010000-10000000-00000000 +// CHECK-INST: smop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x80,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108000 + +smop4a za3.s, z12.b, {z24.b-z25.b} // 10000000-00011000-10000001-10000011 +// CHECK-INST: smop4a za3.s, z12.b, { z24.b, z25.b } +// CHECK-ENCODING: [0x83,0x81,0x18,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80188183 + +smop4a za3.s, z14.b, {z30.b-z31.b} // 10000000-00011110-10000001-11000011 +// CHECK-INST: smop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x81,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e81c3 + +smop4a za0.s, {z0.b-z1.b}, z16.b // 10000000-00000000-10000010-00000000 +// CHECK-INST: smop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x82,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008200 + +smop4a za1.s, {z10.b-z11.b}, z20.b // 10000000-00000100-10000011-01000001 +// CHECK-INST: smop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x83,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80048341 + +smop4a za3.s, {z14.b-z15.b}, z30.b // 10000000-00001110-10000011-11000011 +// CHECK-INST: smop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x83,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e83c3 + +smop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00010000-10000010-00000000 +// CHECK-INST: smop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x82,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108200 + +smop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00010100-10000011-01000001 +// CHECK-INST: smop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x83,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80148341 + +smop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00011110-10000011-11000011 +// CHECK-INST: smop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x83,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e83c3 diff --git a/llvm/test/MC/AArch64/SME2p2/smop4a-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/smop4a-diagnostics.s new file mode 100644 index 0000000000000..01ddbe135c948 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4a-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +smop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4a za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4a za4.s, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4a za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +smop4a za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: smop4a za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: smop4a za0.s, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: smop4a za0.s, z16.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +smop4a za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4a za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za0.s, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: smop4a za0.s, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za0.s, z14.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: smop4a za0.s, z14.b, z14.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, .s => .h, .d => .h + +smop4a za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4a za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: smop4a za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4a za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4a za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: smop4a za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/smop4s-16to32.s b/llvm/test/MC/AArch64/SME2p2/smop4s-16to32.s new file mode 100644 index 0000000000000..41828c97321a8 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4s-16to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4s za0.s, z0.h, z16.h // 10000000-00000000-10000000-00011000 +// CHECK-INST: smop4s za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x80,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008018 + +smop4s za3.s, z12.h, z24.h // 10000000-00001000-10000001-10011011 +// CHECK-INST: smop4s za3.s, z12.h, z24.h +// CHECK-ENCODING: [0x9b,0x81,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8008819b + +smop4s za3.s, z14.h, z30.h // 10000000-00001110-10000001-11011011 +// CHECK-INST: smop4s za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xdb,0x81,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e81db + +smop4s za0.s, z0.h, {z16.h-z17.h} // 10000000-00010000-10000000-00011000 +// CHECK-INST: smop4s za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x80,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108018 + +smop4s za3.s, z12.h, {z24.h-z25.h} // 10000000-00011000-10000001-10011011 +// CHECK-INST: smop4s za3.s, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x9b,0x81,0x18,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8018819b + +smop4s za3.s, z14.h, {z30.h-z31.h} // 10000000-00011110-10000001-11011011 +// CHECK-INST: smop4s za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdb,0x81,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e81db + +smop4s za0.s, {z0.h-z1.h}, z16.h // 10000000-00000000-10000010-00011000 +// CHECK-INST: smop4s za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x82,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008218 + +smop4s za3.s, {z12.h-z13.h}, z24.h // 10000000-00001000-10000011-10011011 +// CHECK-INST: smop4s za3.s, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x9b,0x83,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8008839b + +smop4s za3.s, {z14.h-z15.h}, z30.h // 10000000-00001110-10000011-11011011 +// CHECK-INST: smop4s za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdb,0x83,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e83db + +smop4s za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000000-00010000-10000010-00011000 +// CHECK-INST: smop4s za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x82,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108218 + +smop4s za3.s, {z12.h-z13.h}, {z24.h-z25.h} // 10000000-00011000-10000011-10011011 +// CHECK-INST: smop4s za3.s, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x9b,0x83,0x18,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8018839b + +smop4s za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000000-00011110-10000011-11011011 +// CHECK-INST: smop4s za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdb,0x83,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e83db diff --git a/llvm/test/MC/AArch64/SME2p2/smop4s-64.s b/llvm/test/MC/AArch64/SME2p2/smop4s-64.s new file mode 100644 index 0000000000000..1b2e2637f0119 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4s-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4s za0.d, z0.h, z16.h // 10100000-11000000-00000000-00011000 +// CHECK-INST: smop4s za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0xc0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c00018 + +smop4s za5.d, z10.h, z20.h // 10100000-11000100-00000001-01011101 +// CHECK-INST: smop4s za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x5d,0x01,0xc4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c4015d + +smop4s za7.d, z14.h, z30.h // 10100000-11001110-00000001-11011111 +// CHECK-INST: smop4s za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xdf,0x01,0xce,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ce01df + +smop4s za0.d, z0.h, {z16.h-z17.h} // 10100000-11010000-00000000-00011000 +// CHECK-INST: smop4s za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0xd0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d00018 + +smop4s za5.d, z10.h, {z20.h-z21.h} // 10100000-11010100-00000001-01011101 +// CHECK-INST: smop4s za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x01,0xd4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d4015d + +smop4s za7.d, z14.h, {z30.h-z31.h} // 10100000-11011110-00000001-11011111 +// CHECK-INST: smop4s za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x01,0xde,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0de01df + +smop4s za0.d, {z0.h-z1.h}, z16.h // 10100000-11000000-00000010-00011000 +// CHECK-INST: smop4s za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0xc0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c00218 + +smop4s za5.d, {z10.h-z11.h}, z20.h // 10100000-11000100-00000011-01011101 +// CHECK-INST: smop4s za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x5d,0x03,0xc4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0c4035d + +smop4s za7.d, {z14.h-z15.h}, z30.h // 10100000-11001110-00000011-11011111 +// CHECK-INST: smop4s za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdf,0x03,0xce,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ce03df + +smop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100000-11010000-00000010-00011000 +// CHECK-INST: smop4s za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0xd0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d00218 + +smop4s za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100000-11010100-00000011-01011101 +// CHECK-INST: smop4s za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x03,0xd4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0d4035d + +smop4s za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100000-11011110-00000011-11011111 +// CHECK-INST: smop4s za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x03,0xde,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0de03df diff --git a/llvm/test/MC/AArch64/SME2p2/smop4s-8to32.s b/llvm/test/MC/AArch64/SME2p2/smop4s-8to32.s new file mode 100644 index 0000000000000..43fbda9172866 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4s-8to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +smop4s za0.s, z0.b, z16.b // 10000000-00000000-10000000-00010000 +// CHECK-INST: smop4s za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x10,0x80,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008010 + +smop4s za1.s, z10.b, z20.b // 10000000-00000100-10000001-01010001 +// CHECK-INST: smop4s za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x51,0x81,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80048151 + +smop4s za3.s, z14.b, z30.b // 10000000-00001110-10000001-11010011 +// CHECK-INST: smop4s za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xd3,0x81,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e81d3 + +smop4s za0.s, z0.b, {z16.b-z17.b} // 10000000-00010000-10000000-00010000 +// CHECK-INST: smop4s za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x80,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108010 + +smop4s za1.s, z10.b, {z20.b-z21.b} // 10000000-00010100-10000001-01010001 +// CHECK-INST: smop4s za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x81,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80148151 + +smop4s za3.s, z14.b, {z30.b-z31.b} // 10000000-00011110-10000001-11010011 +// CHECK-INST: smop4s za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x81,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e81d3 + +smop4s za0.s, {z0.b-z1.b}, z16.b // 10000000-00000000-10000010-00010000 +// CHECK-INST: smop4s za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x10,0x82,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80008210 + +smop4s za1.s, {z10.b-z11.b}, z20.b // 10000000-00000100-10000011-01010001 +// CHECK-INST: smop4s za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x51,0x83,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80048351 + +smop4s za3.s, {z14.b-z15.b}, z30.b // 10000000-00001110-10000011-11010011 +// CHECK-INST: smop4s za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xd3,0x83,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e83d3 + +smop4s za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00010000-10000010-00010000 +// CHECK-INST: smop4s za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x82,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80108210 + +smop4s za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00010100-10000011-01010001 +// CHECK-INST: smop4s za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x83,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80148351 + +smop4s za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00011110-10000011-11010011 +// CHECK-INST: smop4s za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x83,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e83d3 diff --git a/llvm/test/MC/AArch64/SME2p2/smop4s-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/smop4s-diagnostics.s new file mode 100644 index 0000000000000..a11402c8c7be6 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/smop4s-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +smop4s za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4s za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4s za4.s, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smop4s za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +smop4s za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: smop4s za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: smop4s za0.s, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: smop4s za0.s, z16.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +smop4s za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4s za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za0.s, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: smop4s za0.s, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za0.s, z14.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: smop4s za0.s, z14.b, z14.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, s => .h, .d => .h + +smop4s za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4s za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: smop4s za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: smop4s za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smop4s za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: smop4s za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4a-32.s b/llvm/test/MC/AArch64/SME2p2/sumop4a-32.s new file mode 100644 index 0000000000000..8633eae24f498 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4a-32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sumop4a za0.s, z0.b, z16.b // 10000000-00100000-10000000-00000000 +// CHECK-INST: sumop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x80,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80208000 + +sumop4a za1.s, z10.b, z20.b // 10000000-00100100-10000001-01000001 +// CHECK-INST: sumop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x81,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80248141 + +sumop4a za3.s, z14.b, z30.b // 10000000-00101110-10000001-11000011 +// CHECK-INST: sumop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x81,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 802e81c3 + +sumop4a za0.s, z0.b, {z16.b-z17.b} // 10000000-00110000-10000000-00000000 +// CHECK-INST: sumop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x80,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80308000 + +sumop4a za1.s, z10.b, {z20.b-z21.b} // 10000000-00110100-10000001-01000001 +// CHECK-INST: sumop4a za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x81,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80348141 + +sumop4a za3.s, z14.b, {z30.b-z31.b} // 10000000-00111110-10000001-11000011 +// CHECK-INST: sumop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x81,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 803e81c3 + +sumop4a za0.s, {z0.b-z1.b}, z16.b // 10000000-00100000-10000010-00000000 +// CHECK-INST: sumop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x82,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80208200 + +sumop4a za1.s, {z10.b-z11.b}, z20.b // 10000000-00100100-10000011-01000001 +// CHECK-INST: sumop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x83,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80248341 + +sumop4a za3.s, {z14.b-z15.b}, z30.b // 10000000-00101110-10000011-11000011 +// CHECK-INST: sumop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x83,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 802e83c3 + +sumop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-10000010-00000000 +// CHECK-INST: sumop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x82,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80308200 + +sumop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-10000011-01000001 +// CHECK-INST: sumop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x83,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80348341 + +sumop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-10000011-11000011 +// CHECK-INST: sumop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x83,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 803e83c3 diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4a-64.s b/llvm/test/MC/AArch64/SME2p2/sumop4a-64.s new file mode 100644 index 0000000000000..53fa6f0892c5c --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4a-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sumop4a za0.d, z0.h, z16.h // 10100000-11100000-00000000-00001000 +// CHECK-INST: sumop4a za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0xe0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e00008 + +sumop4a za5.d, z10.h, z20.h // 10100000-11100100-00000001-01001101 +// CHECK-INST: sumop4a za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x4d,0x01,0xe4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e4014d + +sumop4a za7.d, z14.h, z30.h // 10100000-11101110-00000001-11001111 +// CHECK-INST: sumop4a za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xcf,0x01,0xee,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ee01cf + +sumop4a za0.d, z0.h, {z16.h-z17.h} // 10100000-11110000-00000000-00001000 +// CHECK-INST: sumop4a za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0xf0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f00008 + +sumop4a za5.d, z10.h, {z20.h-z21.h} // 10100000-11110100-00000001-01001101 +// CHECK-INST: sumop4a za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x01,0xf4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f4014d + +sumop4a za7.d, z14.h, {z30.h-z31.h} // 10100000-11111110-00000001-11001111 +// CHECK-INST: sumop4a za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x01,0xfe,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0fe01cf + +sumop4a za0.d, {z0.h-z1.h}, z16.h // 10100000-11100000-00000010-00001000 +// CHECK-INST: sumop4a za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0xe0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e00208 + +sumop4a za5.d, {z10.h-z11.h}, z20.h // 10100000-11100100-00000011-01001101 +// CHECK-INST: sumop4a za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x4d,0x03,0xe4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e4034d + +sumop4a za7.d, {z14.h-z15.h}, z30.h // 10100000-11101110-00000011-11001111 +// CHECK-INST: sumop4a za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcf,0x03,0xee,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ee03cf + +sumop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100000-11110000-00000010-00001000 +// CHECK-INST: sumop4a za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0xf0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f00208 + +sumop4a za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100000-11110100-00000011-01001101 +// CHECK-INST: sumop4a za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x03,0xf4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f4034d + +sumop4a za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100000-11111110-00000011-11001111 +// CHECK-INST: sumop4a za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x03,0xfe,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0fe03cf diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4a-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/sumop4a-diagnostics.s new file mode 100644 index 0000000000000..456aa1ad71310 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4a-diagnostics.s @@ -0,0 +1,68 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +sumop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sumop4a za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sumop4a za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +sumop4a za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: sumop4a za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za0.d, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sumop4a za0.d, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +sumop4a za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: sumop4a za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za0.d, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sumop4a za0.d, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, .d => .h + +sumop4a za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: sumop4a za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: sumop4a za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: sumop4a za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4a za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: sumop4a za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4s-32.s b/llvm/test/MC/AArch64/SME2p2/sumop4s-32.s new file mode 100644 index 0000000000000..be9a25d85a015 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4s-32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sumop4s za0.s, z0.b, z16.b // 10000000-00100000-10000000-00010000 +// CHECK-INST: sumop4s za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x10,0x80,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80208010 + +sumop4s za1.s, z10.b, z20.b // 10000000-00100100-10000001-01010001 +// CHECK-INST: sumop4s za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x51,0x81,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80248151 + +sumop4s za3.s, z14.b, z30.b // 10000000-00101110-10000001-11010011 +// CHECK-INST: sumop4s za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xd3,0x81,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 802e81d3 + +sumop4s za0.s, z0.b, {z16.b-z17.b} // 10000000-00110000-10000000-00010000 +// CHECK-INST: sumop4s za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x80,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80308010 + +sumop4s za1.s, z10.b, {z20.b-z21.b} // 10000000-00110100-10000001-01010001 +// CHECK-INST: sumop4s za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x81,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80348151 + +sumop4s za3.s, z14.b, {z30.b-z31.b} // 10000000-00111110-10000001-11010011 +// CHECK-INST: sumop4s za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x81,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 803e81d3 + +sumop4s za0.s, {z0.b-z1.b}, z16.b // 10000000-00100000-10000010-00010000 +// CHECK-INST: sumop4s za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x10,0x82,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80208210 + +sumop4s za1.s, {z10.b-z11.b}, z20.b // 10000000-00100100-10000011-01010001 +// CHECK-INST: sumop4s za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x51,0x83,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80248351 + +sumop4s za3.s, {z14.b-z15.b}, z30.b // 10000000-00101110-10000011-11010011 +// CHECK-INST: sumop4s za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xd3,0x83,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 802e83d3 + +sumop4s za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-10000010-00010000 +// CHECK-INST: sumop4s za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x82,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80308210 + +sumop4s za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-10000011-01010001 +// CHECK-INST: sumop4s za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x83,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80348351 + +sumop4s za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-10000011-11010011 +// CHECK-INST: sumop4s za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x83,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 803e83d3 diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4s-64.s b/llvm/test/MC/AArch64/SME2p2/sumop4s-64.s new file mode 100644 index 0000000000000..dbb2b8ed53ea2 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4s-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sumop4s za0.d, z0.h, z16.h // 10100000-11100000-00000000-00011000 +// CHECK-INST: sumop4s za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0xe0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e00018 + +sumop4s za5.d, z10.h, z20.h // 10100000-11100100-00000001-01011101 +// CHECK-INST: sumop4s za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x5d,0x01,0xe4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e4015d + +sumop4s za7.d, z14.h, z30.h // 10100000-11101110-00000001-11011111 +// CHECK-INST: sumop4s za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xdf,0x01,0xee,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ee01df + +sumop4s za0.d, z0.h, {z16.h-z17.h} // 10100000-11110000-00000000-00011000 +// CHECK-INST: sumop4s za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0xf0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f00018 + +sumop4s za5.d, z10.h, {z20.h-z21.h} // 10100000-11110100-00000001-01011101 +// CHECK-INST: sumop4s za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x01,0xf4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f4015d + +sumop4s za7.d, z14.h, {z30.h-z31.h} // 10100000-11111110-00000001-11011111 +// CHECK-INST: sumop4s za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x01,0xfe,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0fe01df + +sumop4s za0.d, {z0.h-z1.h}, z16.h // 10100000-11100000-00000010-00011000 +// CHECK-INST: sumop4s za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0xe0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e00218 + +sumop4s za5.d, {z10.h-z11.h}, z20.h // 10100000-11100100-00000011-01011101 +// CHECK-INST: sumop4s za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x5d,0x03,0xe4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0e4035d + +sumop4s za7.d, {z14.h-z15.h}, z30.h // 10100000-11101110-00000011-11011111 +// CHECK-INST: sumop4s za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdf,0x03,0xee,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0ee03df + +sumop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100000-11110000-00000010-00011000 +// CHECK-INST: sumop4s za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0xf0,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f00218 + +sumop4s za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100000-11110100-00000011-01011101 +// CHECK-INST: sumop4s za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x03,0xf4,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0f4035d + +sumop4s za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100000-11111110-00000011-11011111 +// CHECK-INST: sumop4s za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x03,0xfe,0xa0] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a0fe03df diff --git a/llvm/test/MC/AArch64/SME2p2/sumop4s-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/sumop4s-diagnostics.s new file mode 100644 index 0000000000000..39a397d7b5671 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/sumop4s-diagnostics.s @@ -0,0 +1,68 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +sumop4s za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sumop4s za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sumop4s za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +sumop4s za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: sumop4s za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za0.d, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sumop4s za0.d, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +sumop4s za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: sumop4s za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za0.d, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sumop4s za0.d, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, .d => .h + +sumop4s za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: sumop4s za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: sumop4s za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: sumop4s za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sumop4s za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: sumop4s za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/umop4a-16to32.s b/llvm/test/MC/AArch64/SME2p2/umop4a-16to32.s new file mode 100644 index 0000000000000..15490565f8ecf --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4a-16to32.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +umop4a za0.s, z0.h, z16.h // 10000001-00000000-10000000-00001000 +// CHECK-INST: umop4a za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x80,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008008 + +umop4a za3.s, z12.h, z24.h // 10000001-00001000-10000001-10001011 +// CHECK-INST: umop4a za3.s, z12.h, z24.h +// CHECK-ENCODING: [0x8b,0x81,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8108818b + +umop4a za3.s, z14.h, z30.h // 10000001-00001110-10000001-11001011 +// CHECK-INST: umop4a za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xcb,0x81,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e81cb + +umop4a za0.s, z0.h, {z16.h-z17.h} // 10000001-00010000-10000000-00001000 +// CHECK-INST: umop4a za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x80,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108008 + +umop4a za3.s, z12.h, {z24.h-z25.h} // 10000001-00011000-10000001-10001011 +// CHECK-INST: umop4a za3.s, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x8b,0x81,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8118818b + +umop4a za3.s, z14.h, {z30.h-z31.h} // 10000001-00011110-10000001-11001011 +// CHECK-INST: umop4a za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcb,0x81,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e81cb + +umop4a za0.s, {z0.h-z1.h}, z16.h // 10000001-00000000-10000010-00001000 +// CHECK-INST: umop4a za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x82,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008208 + +umop4a za3.s, {z12.h-z13.h}, z24.h // 10000001-00001000-10000011-10001011 +// CHECK-INST: umop4a za3.s, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x8b,0x83,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8108838b + +umop4a za3.s, {z14.h-z15.h}, z30.h // 10000001-00001110-10000011-11001011 +// CHECK-INST: umop4a za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcb,0x83,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e83cb + +umop4a za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00010000-10000010-00001000 +// CHECK-INST: umop4a za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x82,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108208 + +umop4a za3.s, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00011000-10000011-10001011 +// CHECK-INST: umop4a za3.s, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x8b,0x83,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8118838b + +umop4a za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00011110-10000011-11001011 +// CHECK-INST: umop4a za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcb,0x83,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e83cb diff --git a/llvm/test/MC/AArch64/SME2p2/umop4a-64.s b/llvm/test/MC/AArch64/SME2p2/umop4a-64.s new file mode 100644 index 0000000000000..c0f85af6abdbd --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4a-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +umop4a za0.d, z0.h, z16.h // 10100001-11100000-00000000-00001000 +// CHECK-INST: umop4a za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0xe0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e00008 + +umop4a za5.d, z10.h, z20.h // 10100001-11100100-00000001-01001101 +// CHECK-INST: umop4a za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x4d,0x01,0xe4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e4014d + +umop4a za7.d, z14.h, z30.h // 10100001-11101110-00000001-11001111 +// CHECK-INST: umop4a za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xcf,0x01,0xee,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ee01cf + +umop4a za0.d, z0.h, {z16.h-z17.h} // 10100001-11110000-00000000-00001000 +// CHECK-INST: umop4a za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0xf0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f00008 + +umop4a za5.d, z10.h, {z20.h-z21.h} // 10100001-11110100-00000001-01001101 +// CHECK-INST: umop4a za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x01,0xf4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f4014d + +umop4a za7.d, z14.h, {z30.h-z31.h} // 10100001-11111110-00000001-11001111 +// CHECK-INST: umop4a za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x01,0xfe,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1fe01cf + +umop4a za0.d, {z0.h-z1.h}, z16.h // 10100001-11100000-00000010-00001000 +// CHECK-INST: umop4a za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0xe0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e00208 + +umop4a za5.d, {z10.h-z11.h}, z20.h // 10100001-11100100-00000011-01001101 +// CHECK-INST: umop4a za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x4d,0x03,0xe4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e4034d + +umop4a za7.d, {z14.h-z15.h}, z30.h // 10100001-11101110-00000011-11001111 +// CHECK-INST: umop4a za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcf,0x03,0xee,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ee03cf + +umop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100001-11110000-00000010-00001000 +// CHECK-INST: umop4a za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0xf0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f00208 + +umop4a za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100001-11110100-00000011-01001101 +// CHECK-INST: umop4a za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x03,0xf4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f4034d + +umop4a za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100001-11111110-00000011-11001111 +// CHECK-INST: umop4a za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x03,0xfe,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1fe03cf diff --git a/llvm/test/MC/AArch64/SME2p2/umop4a-8to32.s b/llvm/test/MC/AArch64/SME2p2/umop4a-8to32.s new file mode 100644 index 0000000000000..d22d2249709be --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4a-8to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +umop4a za0.s, z0.b, z16.b // 10000001-00100000-10000000-00000000 +// CHECK-INST: umop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x80,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81208000 + +umop4a za1.s, z10.b, z20.b // 10000001-00100100-10000001-01000001 +// CHECK-INST: umop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x81,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81248141 + +umop4a za3.s, z14.b, z30.b // 10000001-00101110-10000001-11000011 +// CHECK-INST: umop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x81,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e81c3 + +umop4a za0.s, z0.b, {z16.b-z17.b} // 10000001-00110000-10000000-00000000 +// CHECK-INST: umop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x80,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81308000 + +umop4a za1.s, z10.b, {z20.b-z21.b} // 10000001-00110100-10000001-01000001 +// CHECK-INST: umop4a za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x81,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81348141 + +umop4a za3.s, z14.b, {z30.b-z31.b} // 10000001-00111110-10000001-11000011 +// CHECK-INST: umop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x81,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e81c3 + +umop4a za0.s, {z0.b-z1.b}, z16.b // 10000001-00100000-10000010-00000000 +// CHECK-INST: umop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x82,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81208200 + +umop4a za1.s, {z10.b-z11.b}, z20.b // 10000001-00100100-10000011-01000001 +// CHECK-INST: umop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x83,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81248341 + +umop4a za3.s, {z14.b-z15.b}, z30.b // 10000001-00101110-10000011-11000011 +// CHECK-INST: umop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x83,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e83c3 + +umop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000001-00110000-10000010-00000000 +// CHECK-INST: umop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x82,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81308200 + +umop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000001-00110100-10000011-01000001 +// CHECK-INST: umop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x83,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81348341 + +umop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000001-00111110-10000011-11000011 +// CHECK-INST: umop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x83,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e83c3 diff --git a/llvm/test/MC/AArch64/SME2p2/umop4a-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/umop4a-diagnostics.s new file mode 100644 index 0000000000000..a522ab1baacda --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4a-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +umop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4a za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4a za4.s, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4a za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +umop4a za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: umop4a za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: umop4a za0.s, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: umop4a za0.s, z16.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +umop4a za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4a za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za0.s, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: umop4a za0.s, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za0.s, z14.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: umop4a za0.s, z14.b, z14.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, s => .h, .d => .h + +umop4a za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4a za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: umop4a za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4a za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4a za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: umop4a za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/umop4s-16to32.s b/llvm/test/MC/AArch64/SME2p2/umop4s-16to32.s new file mode 100644 index 0000000000000..c83925737005e --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4s-16to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +umop4s za0.s, z0.h, z16.h // 10000001-00000000-10000000-00011000 +// CHECK-INST: umop4s za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x80,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008018 + +umop4s za3.s, z12.h, z24.h // 10000001-00001000-10000001-10011011 +// CHECK-INST: umop4s za3.s, z12.h, z24.h +// CHECK-ENCODING: [0x9b,0x81,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8108819b + +umop4s za3.s, z14.h, z30.h // 10000001-00001110-10000001-11011011 +// CHECK-INST: umop4s za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xdb,0x81,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e81db + +umop4s za0.s, z0.h, {z16.h-z17.h} // 10000001-00010000-10000000-00011000 +// CHECK-INST: umop4s za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x80,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108018 + +umop4s za3.s, z12.h, {z24.h-z25.h} // 10000001-00011000-10000001-10011011 +// CHECK-INST: umop4s za3.s, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x9b,0x81,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8118819b + +umop4s za3.s, z14.h, {z30.h-z31.h} // 10000001-00011110-10000001-11011011 +// CHECK-INST: umop4s za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdb,0x81,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e81db + +umop4s za0.s, {z0.h-z1.h}, z16.h // 10000001-00000000-10000010-00011000 +// CHECK-INST: umop4s za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x82,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008218 + +umop4s za3.s, {z12.h-z13.h}, z24.h // 10000001-00001000-10000011-10011011 +// CHECK-INST: umop4s za3.s, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x9b,0x83,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8108839b + +umop4s za3.s, {z14.h-z15.h}, z30.h // 10000001-00001110-10000011-11011011 +// CHECK-INST: umop4s za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdb,0x83,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e83db + +umop4s za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00010000-10000010-00011000 +// CHECK-INST: umop4s za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x82,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108218 + +umop4s za3.s, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00011000-10000011-10011011 +// CHECK-INST: umop4s za3.s, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x9b,0x83,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 8118839b + +umop4s za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00011110-10000011-11011011 +// CHECK-INST: umop4s za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdb,0x83,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e83db diff --git a/llvm/test/MC/AArch64/SME2p2/umop4s-64.s b/llvm/test/MC/AArch64/SME2p2/umop4s-64.s new file mode 100644 index 0000000000000..5f39ca7cf373c --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4s-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +umop4s za0.d, z0.h, z16.h // 10100001-11100000-00000000-00011000 +// CHECK-INST: umop4s za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0xe0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e00018 + +umop4s za5.d, z10.h, z20.h // 10100001-11100100-00000001-01011101 +// CHECK-INST: umop4s za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x5d,0x01,0xe4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e4015d + +umop4s za7.d, z14.h, z30.h // 10100001-11101110-00000001-11011111 +// CHECK-INST: umop4s za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xdf,0x01,0xee,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ee01df + +umop4s za0.d, z0.h, {z16.h-z17.h} // 10100001-11110000-00000000-00011000 +// CHECK-INST: umop4s za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0xf0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f00018 + +umop4s za5.d, z10.h, {z20.h-z21.h} // 10100001-11110100-00000001-01011101 +// CHECK-INST: umop4s za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x01,0xf4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f4015d + +umop4s za7.d, z14.h, {z30.h-z31.h} // 10100001-11111110-00000001-11011111 +// CHECK-INST: umop4s za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x01,0xfe,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1fe01df + +umop4s za0.d, {z0.h-z1.h}, z16.h // 10100001-11100000-00000010-00011000 +// CHECK-INST: umop4s za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0xe0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e00218 + +umop4s za5.d, {z10.h-z11.h}, z20.h // 10100001-11100100-00000011-01011101 +// CHECK-INST: umop4s za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x5d,0x03,0xe4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1e4035d + +umop4s za7.d, {z14.h-z15.h}, z30.h // 10100001-11101110-00000011-11011111 +// CHECK-INST: umop4s za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdf,0x03,0xee,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ee03df + +umop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100001-11110000-00000010-00011000 +// CHECK-INST: umop4s za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0xf0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f00218 + +umop4s za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100001-11110100-00000011-01011101 +// CHECK-INST: umop4s za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x03,0xf4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1f4035d + +umop4s za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100001-11111110-00000011-11011111 +// CHECK-INST: umop4s za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x03,0xfe,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1fe03df diff --git a/llvm/test/MC/AArch64/SME2p2/umop4s-8to32.s b/llvm/test/MC/AArch64/SME2p2/umop4s-8to32.s new file mode 100644 index 0000000000000..74cbffc5ef01d --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4s-8to32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +umop4s za0.s, z0.b, z16.b // 10000001-00100000-10000000-00010000 +// CHECK-INST: umop4s za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x10,0x80,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81208010 + +umop4s za1.s, z10.b, z20.b // 10000001-00100100-10000001-01010001 +// CHECK-INST: umop4s za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x51,0x81,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81248151 + +umop4s za3.s, z14.b, z30.b // 10000001-00101110-10000001-11010011 +// CHECK-INST: umop4s za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xd3,0x81,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e81d3 + +umop4s za0.s, z0.b, {z16.b-z17.b} // 10000001-00110000-10000000-00010000 +// CHECK-INST: umop4s za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x80,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81308010 + +umop4s za1.s, z10.b, {z20.b-z21.b} // 10000001-00110100-10000001-01010001 +// CHECK-INST: umop4s za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x81,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81348151 + +umop4s za3.s, z14.b, {z30.b-z31.b} // 10000001-00111110-10000001-11010011 +// CHECK-INST: umop4s za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x81,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e81d3 + +umop4s za0.s, {z0.b-z1.b}, z16.b // 10000001-00100000-10000010-00010000 +// CHECK-INST: umop4s za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x10,0x82,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81208210 + +umop4s za1.s, {z10.b-z11.b}, z20.b // 10000001-00100100-10000011-01010001 +// CHECK-INST: umop4s za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x51,0x83,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81248351 + +umop4s za3.s, {z14.b-z15.b}, z30.b // 10000001-00101110-10000011-11010011 +// CHECK-INST: umop4s za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xd3,0x83,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e83d3 + +umop4s za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000001-00110000-10000010-00010000 +// CHECK-INST: umop4s za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x82,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81308210 + +umop4s za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000001-00110100-10000011-01010001 +// CHECK-INST: umop4s za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x83,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81348351 + +umop4s za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000001-00111110-10000011-11010011 +// CHECK-INST: umop4s za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x83,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e83d3 diff --git a/llvm/test/MC/AArch64/SME2p2/umop4s-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/umop4s-diagnostics.s new file mode 100644 index 0000000000000..c5f9877522e3d --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/umop4s-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +umop4s za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4s za4.s, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4s za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umop4s za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +umop4s za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: umop4s za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: umop4s za0.s, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: umop4s za0.s, z16.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}} + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +umop4s za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4s za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za0.s, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: umop4s za0.s, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za0.s, z14.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: umop4s za0.s, z14.b, z14.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, s => .h, .d => .h + +umop4s za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4s za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: umop4s za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: umop4s za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umop4s za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: umop4s za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4a-32.s b/llvm/test/MC/AArch64/SME2p2/usmop4a-32.s new file mode 100644 index 0000000000000..2bbddfd1e64e0 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4a-32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +usmop4a za0.s, z0.b, z16.b // 10000001-00000000-10000000-00000000 +// CHECK-INST: usmop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x80,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008000 + +usmop4a za1.s, z10.b, z20.b // 10000001-00000100-10000001-01000001 +// CHECK-INST: usmop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x81,0x04,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81048141 + +usmop4a za3.s, z14.b, z30.b // 10000001-00001110-10000001-11000011 +// CHECK-INST: usmop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x81,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e81c3 + +usmop4a za0.s, z0.b, {z16.b-z17.b} // 10000001-00010000-10000000-00000000 +// CHECK-INST: usmop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x80,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108000 + +usmop4a za1.s, z10.b, {z20.b-z21.b} // 10000001-00010100-10000001-01000001 +// CHECK-INST: usmop4a za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x81,0x14,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81148141 + +usmop4a za3.s, z14.b, {z30.b-z31.b} // 10000001-00011110-10000001-11000011 +// CHECK-INST: usmop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x81,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e81c3 + +usmop4a za0.s, {z0.b-z1.b}, z16.b // 10000001-00000000-10000010-00000000 +// CHECK-INST: usmop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x82,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008200 + +usmop4a za1.s, {z10.b-z11.b}, z20.b // 10000001-00000100-10000011-01000001 +// CHECK-INST: usmop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x83,0x04,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81048341 + +usmop4a za3.s, {z14.b-z15.b}, z30.b // 10000001-00001110-10000011-11000011 +// CHECK-INST: usmop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x83,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e83c3 + +usmop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000001-00010000-10000010-00000000 +// CHECK-INST: usmop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x82,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108200 + +usmop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000001-00010100-10000011-01000001 +// CHECK-INST: usmop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x83,0x14,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81148341 + +usmop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000001-00011110-10000011-11000011 +// CHECK-INST: usmop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x83,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e83c3 diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4a-64.s b/llvm/test/MC/AArch64/SME2p2/usmop4a-64.s new file mode 100644 index 0000000000000..1da7b31d1b94f --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4a-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +usmop4a za0.d, z0.h, z16.h // 10100001-11000000-00000000-00001000 +// CHECK-INST: usmop4a za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0xc0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c00008 + +usmop4a za5.d, z10.h, z20.h // 10100001-11000100-00000001-01001101 +// CHECK-INST: usmop4a za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x4d,0x01,0xc4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c4014d + +usmop4a za7.d, z14.h, z30.h // 10100001-11001110-00000001-11001111 +// CHECK-INST: usmop4a za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xcf,0x01,0xce,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ce01cf + +usmop4a za0.d, z0.h, {z16.h-z17.h} // 10100001-11010000-00000000-00001000 +// CHECK-INST: usmop4a za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0xd0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d00008 + +usmop4a za5.d, z10.h, {z20.h-z21.h} // 10100001-11010100-00000001-01001101 +// CHECK-INST: usmop4a za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x01,0xd4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d4014d + +usmop4a za7.d, z14.h, {z30.h-z31.h} // 10100001-11011110-00000001-11001111 +// CHECK-INST: usmop4a za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x01,0xde,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1de01cf + +usmop4a za0.d, {z0.h-z1.h}, z16.h // 10100001-11000000-00000010-00001000 +// CHECK-INST: usmop4a za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0xc0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c00208 + +usmop4a za5.d, {z10.h-z11.h}, z20.h // 10100001-11000100-00000011-01001101 +// CHECK-INST: usmop4a za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x4d,0x03,0xc4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c4034d + +usmop4a za7.d, {z14.h-z15.h}, z30.h // 10100001-11001110-00000011-11001111 +// CHECK-INST: usmop4a za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xcf,0x03,0xce,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ce03cf + +usmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100001-11010000-00000010-00001000 +// CHECK-INST: usmop4a za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0xd0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d00208 + +usmop4a za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100001-11010100-00000011-01001101 +// CHECK-INST: usmop4a za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x03,0xd4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d4034d + +usmop4a za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100001-11011110-00000011-11001111 +// CHECK-INST: usmop4a za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x03,0xde,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1de03cf diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4a-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/usmop4a-diagnostics.s new file mode 100644 index 0000000000000..18d9963a3274f --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4a-diagnostics.s @@ -0,0 +1,68 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +usmop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: usmop4a za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: usmop4a za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +usmop4a za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: usmop4a za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za0.d, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: usmop4a za0.d, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +usmop4a za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: usmop4a za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za0.d, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: usmop4a za0.d, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, .d => .h + +usmop4a za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: usmop4a za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: usmop4a za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: usmop4a za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4a za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: usmop4a za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4s-32.s b/llvm/test/MC/AArch64/SME2p2/usmop4s-32.s new file mode 100644 index 0000000000000..e8cc918e55d02 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4s-32.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +usmop4s za0.s, z0.b, z16.b // 10000001-00000000-10000000-00010000 +// CHECK-INST: usmop4s za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x10,0x80,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008010 + +usmop4s za1.s, z10.b, z20.b // 10000001-00000100-10000001-01010001 +// CHECK-INST: usmop4s za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x51,0x81,0x04,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81048151 + +usmop4s za3.s, z14.b, z30.b // 10000001-00001110-10000001-11010011 +// CHECK-INST: usmop4s za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xd3,0x81,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e81d3 + +usmop4s za0.s, z0.b, {z16.b-z17.b} // 10000001-00010000-10000000-00010000 +// CHECK-INST: usmop4s za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x80,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108010 + +usmop4s za1.s, z10.b, {z20.b-z21.b} // 10000001-00010100-10000001-01010001 +// CHECK-INST: usmop4s za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x81,0x14,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81148151 + +usmop4s za3.s, z14.b, {z30.b-z31.b} // 10000001-00011110-10000001-11010011 +// CHECK-INST: usmop4s za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x81,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e81d3 + +usmop4s za0.s, {z0.b-z1.b}, z16.b // 10000001-00000000-10000010-00010000 +// CHECK-INST: usmop4s za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x10,0x82,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81008210 + +usmop4s za1.s, {z10.b-z11.b}, z20.b // 10000001-00000100-10000011-01010001 +// CHECK-INST: usmop4s za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x51,0x83,0x04,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81048351 + +usmop4s za3.s, {z14.b-z15.b}, z30.b // 10000001-00001110-10000011-11010011 +// CHECK-INST: usmop4s za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xd3,0x83,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 810e83d3 + +usmop4s za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000001-00010000-10000010-00010000 +// CHECK-INST: usmop4s za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x10,0x82,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81108210 + +usmop4s za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000001-00010100-10000011-01010001 +// CHECK-INST: usmop4s za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x51,0x83,0x14,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81148351 + +usmop4s za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000001-00011110-10000011-11010011 +// CHECK-INST: usmop4s za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xd3,0x83,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 811e83d3 diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4s-64.s b/llvm/test/MC/AArch64/SME2p2/usmop4s-64.s new file mode 100644 index 0000000000000..22df9e07158d2 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4s-64.s @@ -0,0 +1,85 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-i16i64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +usmop4s za0.d, z0.h, z16.h // 10100001-11000000-00000000-00011000 +// CHECK-INST: usmop4s za0.d, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0xc0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c00018 + +usmop4s za5.d, z10.h, z20.h // 10100001-11000100-00000001-01011101 +// CHECK-INST: usmop4s za5.d, z10.h, z20.h +// CHECK-ENCODING: [0x5d,0x01,0xc4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c4015d + +usmop4s za7.d, z14.h, z30.h // 10100001-11001110-00000001-11011111 +// CHECK-INST: usmop4s za7.d, z14.h, z30.h +// CHECK-ENCODING: [0xdf,0x01,0xce,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ce01df + +usmop4s za0.d, z0.h, {z16.h-z17.h} // 10100001-11010000-00000000-00011000 +// CHECK-INST: usmop4s za0.d, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0xd0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d00018 + +usmop4s za5.d, z10.h, {z20.h-z21.h} // 10100001-11010100-00000001-01011101 +// CHECK-INST: usmop4s za5.d, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x01,0xd4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d4015d + +usmop4s za7.d, z14.h, {z30.h-z31.h} // 10100001-11011110-00000001-11011111 +// CHECK-INST: usmop4s za7.d, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x01,0xde,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1de01df + +usmop4s za0.d, {z0.h-z1.h}, z16.h // 10100001-11000000-00000010-00011000 +// CHECK-INST: usmop4s za0.d, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0xc0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c00218 + +usmop4s za5.d, {z10.h-z11.h}, z20.h // 10100001-11000100-00000011-01011101 +// CHECK-INST: usmop4s za5.d, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x5d,0x03,0xc4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1c4035d + +usmop4s za7.d, {z14.h-z15.h}, z30.h // 10100001-11001110-00000011-11011111 +// CHECK-INST: usmop4s za7.d, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xdf,0x03,0xce,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1ce03df + +usmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} // 10100001-11010000-00000010-00011000 +// CHECK-INST: usmop4s za0.d, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0xd0,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d00218 + +usmop4s za5.d, {z10.h-z11.h}, {z20.h-z21.h} // 10100001-11010100-00000011-01011101 +// CHECK-INST: usmop4s za5.d, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x03,0xd4,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1d4035d + +usmop4s za7.d, {z14.h-z15.h}, {z30.h-z31.h} // 10100001-11011110-00000011-11011111 +// CHECK-INST: usmop4s za7.d, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x03,0xde,0xa1] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: a1de03df diff --git a/llvm/test/MC/AArch64/SME2p2/usmop4s-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/usmop4s-diagnostics.s new file mode 100644 index 0000000000000..07353b6350149 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/usmop4s-diagnostics.s @@ -0,0 +1,68 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-i16i64 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid tile +// +// expected: .s => za0-za3, .d => za0-za7 + +usmop4s za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: usmop4s za4.s, z0.b, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za8.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: usmop4s za8.d, z0.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid first operand (expected z0..z15) + +usmop4s za0.d, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: usmop4s za0.d, z16.h, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za0.d, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: usmop4s za0.d, {z16.h-z17.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid second operand (expected z16..z31) + +usmop4s za0.d, z14.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: usmop4s za0.d, z14.h, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za0.d, z14.h, {z14.h-z15.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: usmop4s za0.d, z14.h, {z14.h-z15.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid ZPR type suffix +// +// expected: .s => .b, .d => .h + +usmop4s za3.s, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b +// CHECK-NEXT: usmop4s za3.s, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za3.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b +// CHECK-NEXT: usmop4s za3.s, z0.b, z16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za3.d, z0.h, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h +// CHECK-NEXT: usmop4s za3.d, z0.h, z16.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usmop4s za3.d, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h +// CHECK-NEXT: usmop4s za3.d, z0.s, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: