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Merged
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Oct 22, 2024
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[ARM] Use proper types for these records. #113370

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16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMInstrMVE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1998,7 +1998,7 @@ class MVE_VQxDMULH_Base<string iname, string suffix, bits<2> size, bit rounding,
def MVEvqdmulh : SDNode<"ARMISD::VQDMULH", SDTIntBinOp>;

multiclass MVE_VQxDMULH_m<string iname, MVEVectorVTInfo VTI,
SDNode Op, Intrinsic unpred_int, Intrinsic pred_int,
SDPatternOperator Op, Intrinsic unpred_int, Intrinsic pred_int,
bit rounding> {
def "" : MVE_VQxDMULH_Base<iname, VTI.Suffix, VTI.Size, rounding>;
defvar Inst = !cast<Instruction>(NAME);
Expand Down Expand Up @@ -2199,7 +2199,7 @@ def subnsw : PatFrag<(ops node:$lhs, node:$rhs),
}]>;

multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI, SDNode Op,
SDNode unpred_op, Intrinsic PredInt> {
SDPatternOperator unpred_op, Intrinsic PredInt> {
def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
Expand Down Expand Up @@ -2303,7 +2303,7 @@ class MVE_VHSUB_<string suffix, bit U, bits<2> size,
: MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;

multiclass MVE_VHADD_m<MVEVectorVTInfo VTI, SDNode Op,
SDNode unpred_op, Intrinsic PredInt, PatFrag add_op,
SDPatternOperator unpred_op, Intrinsic PredInt, PatFrag add_op,
SDNode shift_op> {
def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
Expand Down Expand Up @@ -2335,7 +2335,7 @@ defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16, avgflooru, addnuw, ARMvshruImm>;
defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32, avgflooru, addnuw, ARMvshruImm>;

multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
SDNode unpred_op, Intrinsic pred_int, PatFrag sub_op,
SDPatternOperator unpred_op, Intrinsic pred_int, PatFrag sub_op,
SDNode shift_op> {
def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
Expand Down Expand Up @@ -4794,7 +4794,7 @@ class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
let validForTailPredication = 1;
}

multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDNode unpred_op,
multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDPatternOperator unpred_op,
Intrinsic PredInt, bit round> {
def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
defvar Inst = !cast<Instruction>(NAME);
Expand Down Expand Up @@ -5370,8 +5370,8 @@ class MVE_VxADDSUB_qr<string iname, string suffix,
let validForTailPredication = 1;
}

multiclass MVE_VHADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract, SDNode Op,
Intrinsic unpred_int, Intrinsic pred_int, PatFrag add_op, PatFrag shift_op> {
multiclass MVE_VHADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract, SDPatternOperator Op,
Intrinsic unpred_int, Intrinsic pred_int, PatFrag add_op, SDNode shift_op> {
def "" : MVE_VxADDSUB_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, subtract, VTI.Size>;
defm : MVE_TwoOpPatternDup<VTI, Op, pred_int, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
defm : MVE_vec_scalar_int_pat_m<!cast<Instruction>(NAME),
Expand Down Expand Up @@ -5576,7 +5576,7 @@ class MVE_VxxMUL_qr<string iname, string suffix,
}

multiclass MVE_VxxMUL_qr_m<string iname, MVEVectorVTInfo VTI, bit bit_28,
PatFrag Op, Intrinsic int_unpred, Intrinsic int_pred> {
SDPatternOperator Op, Intrinsic int_unpred, Intrinsic int_pred> {
def "" : MVE_VxxMUL_qr<iname, VTI.Suffix, bit_28, VTI.Size, VTI.Size>;

let Predicates = [HasMVEInt] in {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMInstrNEON.td
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Expand Up @@ -4906,7 +4906,7 @@ let Predicates = [HasMatMulInt8] in {
}

multiclass SUDOTLane<bit Q, RegisterClass RegTy, ValueType AccumTy, ValueType InputTy, dag RHS>
: N3VMixedDotLane<Q, 1, "vsudot", "u8", RegTy, AccumTy, InputTy, null_frag, null_frag> {
: N3VMixedDotLane<Q, 1, "vsudot", "u8", RegTy, AccumTy, InputTy, null_frag, (ins)> {
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@davemgreen davemgreen Oct 22, 2024

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Is this an empty DAG?

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@jofrn jofrn Oct 22, 2024 •
edited
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Yes. Thanks! :)

def : Pat<
(AccumTy (int_arm_neon_usdot (AccumTy RegTy:$Vd),
(InputTy (bitconvert (AccumTy
Expand Down
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