From 48272655e2cbb488b536e249b7a6e71934180d78 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 29 Oct 2024 22:50:00 -0700 Subject: [PATCH 1/3] [RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. We need an implicit FRM read operand anytime the rounding mode is dynamic. The post isel hook is responsible for this when isel creates an instruction with dynamic rounding mode. Add a MachineVerifier check to verify the operand is present. --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 7 +++++++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 17 ++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 0cfe4eb063485..adc37adb39d6c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2617,6 +2617,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, } } + if (int Idx = RISCVII::getFRMOpNum(Desc); + Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN && + !MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { + ErrInfo = "dynamic rounding mode should read FRM"; + return false; + } + return true; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index af4f653f57afd..f7472cdbf8c21 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -6471,7 +6471,7 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM; //===----------------------------------------------------------------------===// // 13.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in { +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM; } @@ -6504,7 +6504,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; //===----------------------------------------------------------------------===// // 13.8. Vector Floating-Point Square-Root Instruction //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in defm PseudoVFSQRT : VPseudoVSQR_V_RM; //===----------------------------------------------------------------------===// @@ -6516,7 +6516,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V; //===----------------------------------------------------------------------===// // 13.10. Vector Floating-Point Reciprocal Estimate Instruction //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in defm PseudoVFREC7 : VPseudoVRCP_V_RM; //===----------------------------------------------------------------------===// @@ -6628,9 +6628,10 @@ defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W; defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W; -let hasSideEffects = 0, hasPostISelHook = 1 in +let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; +} defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; } // mayRaiseFPException = true @@ -6666,8 +6667,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// // 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, - hasSideEffects = 0 in { +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM; defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM; } @@ -6679,9 +6679,8 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS; //===----------------------------------------------------------------------===// // 14.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let IsRVVWideningReduction = 1, - hasSideEffects = 0, - mayRaiseFPException = true in { +let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true, + hasPostISelHook = 1 in { defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM; defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM; } From 15f51444ad0652dedf035573d70acdaa9487e9d4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 30 Oct 2024 11:15:05 -0700 Subject: [PATCH 2/3] [RISCV] Remove duplicate vector conversion pseudos. These pseudos used to be handled by CustomInserter to insert the rounding mode change for vector ceil, floor, etc. At some point they were changed to use the InsertReadWriteCSR pass instead of the custom inserter. I believe that makes them redundant with the pseudos used by the RVV intrinsics with rounding mode operand. --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 114 ------------------ .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 20 +-- 2 files changed, 10 insertions(+), 124 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 31f535484c5a7..1ccff75afd09a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1130,46 +1130,6 @@ class VPseudoUnaryMask_NoExcept TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = !interleave([Constraint, "$rd = $passthru"], ","); - let TargetOverlapConstraintType = TargetConstraintType; - let HasVLOp = 1; - let HasSEWOp = 1; - let HasVecPolicyOp = 1; - let HasRoundModeOp = 1; -} - -class VPseudoUnaryMask_FRM TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, ixlenimm:$frm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = !interleave([Constraint, "$rd = $passthru"], ","); - let TargetOverlapConstraintType = TargetConstraintType; - let HasVLOp = 1; - let HasSEWOp = 1; - let HasVecPolicyOp = 1; - let UsesMaskPolicy = 1; - let HasRoundModeOp = 1; -} - class VPseudoUnaryNoMaskGPROut : Pseudo<(outs GPR:$rd), (ins VR:$rs2, AVL:$vl, sew:$sew), []>, @@ -3574,23 +3534,6 @@ multiclass VPseudoConversionRoundingMode TargetConstraintType = 1> { - let VLMul = MInfo.value, SEW=sew in { - defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); - def suffix : VPseudoUnaryNoMask_FRM; - def suffix # "_MASK" : VPseudoUnaryMask_FRM, - RISCVMaskedPseudo; - } -} - multiclass VPseudoConversionNoExcept, - SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVFROUND_NOEXCEPT_V { foreach m = MxListF in { defm _V : VPseudoConversionNoExcept, @@ -3641,15 +3576,6 @@ multiclass VPseudoVCVTF_V_RM { } } -multiclass VPseudoVCVTF_RM_V { - foreach m = MxListF in { - foreach e = SchedSEWSet.val in - defm _V : VPseudoConversionRM, - SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e, - forcePassthruRead=true>; - } -} - multiclass VPseudoVWCVTI_V { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -3668,15 +3594,6 @@ multiclass VPseudoVWCVTI_V_RM { } } -multiclass VPseudoVWCVTI_RM_V { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListFW in { - defm _V : VPseudoConversionRM, - SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVWCVTF_V { defvar constraint = "@earlyclobber $rd"; foreach m = MxListW in { @@ -3717,15 +3634,6 @@ multiclass VPseudoVNCVTI_W_RM { } } -multiclass VPseudoVNCVTI_RM_W { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListW in { - defm _W : VPseudoConversionRM, - SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVNCVTF_W_RM { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -3738,17 +3646,6 @@ multiclass VPseudoVNCVTF_W_RM { } } -multiclass VPseudoVNCVTF_RM_W { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListFW in { - foreach e = SchedSEWSet.val in - defm _W : VPseudoConversionRM, - SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e, - forcePassthruRead=true>; - } -} - multiclass VPseudoVNCVTD_W { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -6579,9 +6476,6 @@ defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM; defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM; } -defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V; -defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V; - defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V; defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V; @@ -6590,8 +6484,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM; defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM; } -defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V; -defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V; } // mayRaiseFPException = true //===----------------------------------------------------------------------===// @@ -6602,8 +6494,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM; defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM; } -defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V; -defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V; defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V; defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V; @@ -6623,8 +6513,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM; defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM; } -defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W; -defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W; defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W; defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W; @@ -6633,8 +6521,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; } -defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W; -defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W; let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 18749f00a10a5..33e1ed120cd08 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2639,8 +2639,8 @@ foreach fvti = AllFloatVectors in { // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions defm : VPatConvertFP2IVL_V_RM; defm : VPatConvertFP2IVL_V_RM; -defm : VPatConvertFP2I_RM_VL_V; -defm : VPatConvertFP2I_RM_VL_V; +defm : VPatConvertFP2I_RM_VL_V; +defm : VPatConvertFP2I_RM_VL_V; defm : VPatConvertFP2IVL_V; defm : VPatConvertFP2IVL_V; @@ -2648,14 +2648,14 @@ defm : VPatConvertFP2IVL_V; defm : VPatConvertI2FPVL_V_RM; defm : VPatConvertI2FPVL_V_RM; -defm : VPatConvertI2FP_RM_VL_V; -defm : VPatConvertI2FP_RM_VL_V; +defm : VPatConvertI2FP_RM_VL_V; +defm : VPatConvertI2FP_RM_VL_V; // 13.18. Widening Floating-Point/Integer Type-Convert Instructions defm : VPatWConvertFP2IVL_V_RM; defm : VPatWConvertFP2IVL_V_RM; -defm : VPatWConvertFP2I_RM_VL_V; -defm : VPatWConvertFP2I_RM_VL_V; +defm : VPatWConvertFP2I_RM_VL_V; +defm : VPatWConvertFP2I_RM_VL_V; defm : VPatWConvertFP2IVL_V; defm : VPatWConvertFP2IVL_V; @@ -2696,8 +2696,8 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions defm : VPatNConvertFP2IVL_W_RM; defm : VPatNConvertFP2IVL_W_RM; -defm : VPatNConvertFP2I_RM_VL_W; -defm : VPatNConvertFP2I_RM_VL_W; +defm : VPatNConvertFP2I_RM_VL_W; +defm : VPatNConvertFP2I_RM_VL_W; defm : VPatNConvertFP2IVL_W; defm : VPatNConvertFP2IVL_W; @@ -2705,8 +2705,8 @@ defm : VPatNConvertFP2IVL_W; defm : VPatNConvertI2FPVL_W_RM; -defm : VPatNConvertI2FP_RM_VL_W; -defm : VPatNConvertI2FP_RM_VL_W; +defm : VPatNConvertI2FP_RM_VL_W; +defm : VPatNConvertI2FP_RM_VL_W; foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; From 3ea90bc5c75cbb88bb7dcfb5dc85cceeefdc30ef Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 30 Oct 2024 14:12:12 -0700 Subject: [PATCH 3/3] [RISCV] Remove VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN rounding mode. Not completely happy with the hack to RISCVTargetLowering::lowerVPOp. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 30 ++++----- llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 - .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 67 ------------------- 3 files changed, 15 insertions(+), 84 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index af7a39b2580a3..8816d17921d2b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -3030,6 +3030,7 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) { case ISD::VP_FROUND: return RISCVFPRndMode::RMM; case ISD::FRINT: + case ISD::VP_FRINT: return RISCVFPRndMode::DYN; } @@ -3101,6 +3102,8 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG, switch (Op.getOpcode()) { default: llvm_unreachable("Unexpected opcode"); + case ISD::FRINT: + case ISD::VP_FRINT: case ISD::FCEIL: case ISD::VP_FCEIL: case ISD::FFLOOR: @@ -3120,10 +3123,6 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG, Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, Mask, VL); break; - case ISD::FRINT: - case ISD::VP_FRINT: - Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL); - break; case ISD::FNEARBYINT: case ISD::VP_FNEARBYINT: Truncated = DAG.getNode(RISCVISD::VFROUND_NOEXCEPT_VL, DL, ContainerVT, Src, @@ -3294,8 +3293,10 @@ static SDValue lowerVectorXRINT(SDValue Op, SelectionDAG &DAG, } auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); - SDValue Truncated = - DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, ContainerVT, Src, Mask, VL); + SDValue Truncated = DAG.getNode( + RISCVISD::VFCVT_RM_X_F_VL, DL, ContainerVT, Src, Mask, + DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, Subtarget.getXLenVT()), + VL); if (!VT.isFixedLengthVector()) return Truncated; @@ -6170,7 +6171,7 @@ static unsigned getRISCVVLOp(SDValue Op) { case ISD::VP_LRINT: case ISD::LLRINT: case ISD::VP_LLRINT: - return RISCVISD::VFCVT_X_F_VL; + return RISCVISD::VFCVT_RM_X_F_VL; } // clang-format on #undef OP_CASE @@ -6183,7 +6184,7 @@ static bool hasPassthruOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 130 && + 128 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -6209,7 +6210,7 @@ static bool hasMaskOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 130 && + 128 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -11549,6 +11550,11 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const { } } } + // VFCVT_RM_X_F_VL requires a rounding mode to be injected before the VL. + if (RISCVISDOpc == RISCVISD::VFCVT_RM_X_F_VL && + ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) == OpIdx.index()) + Ops.push_back(DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, + Subtarget.getXLenVT())); // Pass through operands which aren't fixed-length vectors. if (!V.getValueType().isFixedLengthVector()) { Ops.push_back(V); @@ -15710,10 +15716,6 @@ static SDValue performFP_TO_INTCombine(SDNode *N, unsigned Opc = IsSigned ? RISCVISD::VFCVT_RTZ_X_F_VL : RISCVISD::VFCVT_RTZ_XU_F_VL; FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL); - } else if (FRM == RISCVFPRndMode::DYN) { - unsigned Opc = - IsSigned ? RISCVISD::VFCVT_X_F_VL : RISCVISD::VFCVT_XU_F_VL; - FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL); } else { unsigned Opc = IsSigned ? RISCVISD::VFCVT_RM_X_F_VL : RISCVISD::VFCVT_RM_XU_F_VL; @@ -20277,8 +20279,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL) NODE_NAME_CASE(VFCVT_RM_X_F_VL) NODE_NAME_CASE(VFCVT_RM_XU_F_VL) - NODE_NAME_CASE(VFCVT_X_F_VL) - NODE_NAME_CASE(VFCVT_XU_F_VL) NODE_NAME_CASE(VFROUND_NOEXCEPT_VL) NODE_NAME_CASE(SINT_TO_FP_VL) NODE_NAME_CASE(UINT_TO_FP_VL) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 0b07ad7d7a423..9ae70d257fa44 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -307,8 +307,6 @@ enum NodeType : unsigned { FCOPYSIGN_VL, // Has a passthru operand VFCVT_RTZ_X_F_VL, VFCVT_RTZ_XU_F_VL, - VFCVT_X_F_VL, - VFCVT_XU_F_VL, VFROUND_NOEXCEPT_VL, VFCVT_RM_X_F_VL, // Has a rounding mode operand. VFCVT_RM_XU_F_VL, // Has a rounding mode operand. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 33e1ed120cd08..9d434cef5a96f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -270,8 +270,6 @@ def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [ SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>; // Float -> Int -def riscv_vfcvt_xu_f_vl : SDNode<"RISCVISD::VFCVT_XU_F_VL", SDT_RISCVFP2IOp_VL>; -def riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVFP2IOp_VL>; def riscv_vfcvt_rm_xu_f_vl : SDNode<"RISCVISD::VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>; def riscv_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>; @@ -1206,24 +1204,6 @@ multiclass VPatConvertFP2IVL_V { } } -multiclass VPatConvertFP2IVL_V_RM { - foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), - (fvti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#ivti.LMul.MX#"_MASK") - (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, - (fvti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, ivti.Log2SEW, TA_MA)>; - } -} - multiclass VPatConvertFP2I_RM_VL_V { foreach fvti = AllFloatVectors in { @@ -1289,25 +1269,6 @@ multiclass VPatWConvertFP2IVL_V } } -multiclass VPatWConvertFP2IVL_V_RM { - foreach fvtiToFWti = AllWidenableFloatVectors in { - defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), - (fvti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#fvti.LMul.MX#"_MASK") - (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, - (fvti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, fvti.Log2SEW, TA_MA)>; - } -} - multiclass VPatWConvertFP2I_RM_VL_V { foreach fvtiToFWti = AllWidenableFloatVectors in { @@ -1361,28 +1322,6 @@ multiclass VPatNConvertFP2IVL_W { - // Reuse the same list of types used in the widening nodes, but just swap the - // direction of types around so we're converting from Wti -> Vti - foreach vtiToWti = AllWidenableIntToFloatVectors in { - defvar vti = vtiToWti.Vti; - defvar fwti = vtiToWti.Wti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), - (fwti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#vti.LMul.MX#"_MASK") - (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, - (fwti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, vti.Log2SEW, TA_MA)>; - } -} - multiclass VPatNConvertFP2I_RM_VL_W { foreach vtiToWti = AllWidenableIntToFloatVectors in { defvar vti = vtiToWti.Vti; @@ -2637,8 +2576,6 @@ foreach fvti = AllFloatVectors in { } // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions -defm : VPatConvertFP2IVL_V_RM; -defm : VPatConvertFP2IVL_V_RM; defm : VPatConvertFP2I_RM_VL_V; defm : VPatConvertFP2I_RM_VL_V; @@ -2652,8 +2589,6 @@ defm : VPatConvertI2FP_RM_VL_V; defm : VPatConvertI2FP_RM_VL_V; // 13.18. Widening Floating-Point/Integer Type-Convert Instructions -defm : VPatWConvertFP2IVL_V_RM; -defm : VPatWConvertFP2IVL_V_RM; defm : VPatWConvertFP2I_RM_VL_V; defm : VPatWConvertFP2I_RM_VL_V; @@ -2694,8 +2629,6 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { } // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions -defm : VPatNConvertFP2IVL_W_RM; -defm : VPatNConvertFP2IVL_W_RM; defm : VPatNConvertFP2I_RM_VL_W; defm : VPatNConvertFP2I_RM_VL_W;