From 9c2d608630e7e71216a37ac99fe1ab5da94e530b Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 30 Oct 2024 15:17:02 -0700 Subject: [PATCH 1/2] [RISCV] Split the VPseudo opcode for VSHA2MS by SEW The vsha2ms.vv from Zvknh[ab] currently supports both SEW=32 and SEW=64. It might have different performance characteristics depending on the SEW on some processors. This patch splits these two different SEWs into their own VPsuedo opcodes and scheduling classes. This is effectively a NFC change. --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 9 +++--- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 30 +++++++++++-------- llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 5 ++-- llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 5 ++-- llvm/lib/Target/RISCV/RISCVScheduleZvk.td | 8 ++--- 5 files changed, 33 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index d5b0fa340684b..be8bc94a76ff0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -4454,21 +4454,22 @@ class VPatTernaryNoMaskWithPolicy : + DAGOperand op2_kind, + bit sew_aware = false> : Pat<(result_type (!cast(intrinsic) (result_type result_reg_class:$rs3), (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), VLOpFrag, (XLenVT timm:$policy))), - (!cast(inst#"_"#kind#"_"#vlmul.MX) + (!cast(inst#"_"#kind#"_"#vlmul.MX#!if(sew_aware, "_E"#!shl(1, log2sew), "")) result_reg_class:$rs3, (op1_type op1_reg_class:$rs1), op2_kind:$rs2, - GPR:$vl, sew, (XLenVT timm:$policy))>; + GPR:$vl, log2sew, (XLenVT timm:$policy))>; class VPatTernaryNoMaskWithPolicyRoundingMode { - let VLMul = MInfo.value in - def "_" # MInfo.MX : VPseudoTernaryNoMask_Zvk; + LMULInfo MInfo, int sew = 0> { + let VLMul = MInfo.value, SEW = sew in { + defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); + def suffix : VPseudoTernaryNoMask_Zvk; + } } multiclass VPseudoBinaryV_V_NoMask_Zvk { @@ -348,12 +350,12 @@ multiclass VPseudoVSHA2CL { } } -multiclass VPseudoVSHA2MS { - foreach m = MxListVF4 in { +multiclass VPseudoVSHA2MS { + foreach m = !if(!eq(sew, 64), MxListVF8, MxListVF4) in { defvar mx = m.MX; - defm _VV : VPseudoTernaryNoMask_Zvk, + defm _VV : VPseudoTernaryNoMask_Zvk, SchedTernary<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV", - "ReadVSHA2MSV", mx>; + "ReadVSHA2MSV", mx, sew>; } } @@ -564,7 +566,9 @@ let Predicates = [HasStdExtZvkned] in { let Predicates = [HasStdExtZvknhaOrZvknhb] in { defm PseudoVSHA2CH : VPseudoVSHA2CH; defm PseudoVSHA2CL : VPseudoVSHA2CL; - defm PseudoVSHA2MS : VPseudoVSHA2MS; + defm PseudoVSHA2MS : VPseudoVSHA2MS; + let Predicates = [HasStdExtZvknhb] in + defm PseudoVSHA2MS : VPseudoVSHA2MS; } // Predicates = [HasStdExtZvknhaOrZvknhb] let Predicates = [HasStdExtZvksed] in { @@ -944,12 +948,14 @@ multiclass VPatUnaryV_V_S_NoMask_Zvk vtilist> { + list vtilist, + bit isSEWAware = false> { foreach vti = vtilist in def : VPatTernaryNoMaskWithPolicy; + vti.RegClass, vti.RegClass, + sew_aware = isSEWAware>; } multiclass VPatBinaryV_VI_NoMask; defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH", I32IntegerVectors>; - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, isSEWAware=true>; } // Predicates = [HasStdExtZvknha] let Predicates = [HasStdExtZvknhb] in { defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32I64IntegerVectors>; defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH", I32I64IntegerVectors>; - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32I64IntegerVectors>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32I64IntegerVectors, isSEWAware=true>; } // Predicates = [HasStdExtZvknhb] let Predicates = [HasStdExtZvksed] in { diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index 7a54d2fe10808..1af89903e0068 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -883,7 +883,8 @@ foreach mx = SchedMxList in { let Latency = 3, ReleaseAtCycles = [LMulLat] in { defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP400VEXQ0], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP400VEXQ0], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP400VEXQ0], mx, IsWorstCase>; + foreach sew = !listremove(SchedSEWSet.val, [8, 16]) in + defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>; } // Zvkned let Latency = 2, ReleaseAtCycles = [LMulLat] in { @@ -1213,7 +1214,7 @@ defm "" : LMULReadAdvance<"ReadVGMULV", 0>; // Zvknha or Zvknhb defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; -defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>; // Zvkned defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index c685a6d2b094b..51aa003139fba 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -791,7 +791,8 @@ foreach mx = SchedMxList in { let Latency = 3, ReleaseAtCycles = [LMulLat] in { defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>; + foreach sew = !listremove(SchedSEWSet.val, [8, 16]) in + defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>; } // Zvkned let Latency = 2, ReleaseAtCycles = [LMulLat] in { @@ -1119,7 +1120,7 @@ defm "" : LMULReadAdvance<"ReadVGMULV", 0>; // Zvknha or Zvknhb defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; -defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>; // Zvkned defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleZvk.td b/llvm/lib/Target/RISCV/RISCVScheduleZvk.td index 640c456322f02..62d9bab0fac85 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleZvk.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleZvk.td @@ -36,7 +36,7 @@ defm "" : LMULSchedWrites<"WriteVGMULV">; /// Zvknha or Zvknhb extensions defm "" : LMULSchedWrites<"WriteVSHA2CHV">; defm "" : LMULSchedWrites<"WriteVSHA2CLV">; -defm "" : LMULSchedWrites<"WriteVSHA2MSV">; +defm "" : LMULSEWSchedWrites<"WriteVSHA2MSV">; /// Zvkned extension defm "" : LMULSchedWrites<"WriteVAESMVV">; @@ -79,7 +79,7 @@ defm "" : LMULSchedReads<"ReadVGMULV">; /// Zvknha or Zvknhb extensions defm "" : LMULSchedReads<"ReadVSHA2CHV">; defm "" : LMULSchedReads<"ReadVSHA2CLV">; -defm "" : LMULSchedReads<"ReadVSHA2MSV">; +defm "" : LMULSEWSchedReads<"ReadVSHA2MSV">; /// Zvkned extension defm "" : LMULSchedReads<"ReadVAESMVV">; @@ -153,11 +153,11 @@ multiclass UnsupportedSchedZvknhaOrZvknhb { let Unsupported = true in { defm "" : LMULWriteRes<"WriteVSHA2CHV", []>; defm "" : LMULWriteRes<"WriteVSHA2CLV", []>; -defm "" : LMULWriteRes<"WriteVSHA2MSV", []>; +defm "" : LMULSEWWriteRes<"WriteVSHA2MSV", []>; defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; -defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>; } } From f97b42d691a8bbd0f16cc624b543151bb00ec286 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 30 Oct 2024 16:24:10 -0700 Subject: [PATCH 2/2] fixup! [RISCV] Split the VPseudo opcode for VSHA2MS by SEW --- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 4 ++-- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index be8bc94a76ff0..347fc0e2775c8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -4459,13 +4459,13 @@ class VPatTernaryNoMaskWithPolicy : + bit isSEWAware = false> : Pat<(result_type (!cast(intrinsic) (result_type result_reg_class:$rs3), (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), VLOpFrag, (XLenVT timm:$policy))), - (!cast(inst#"_"#kind#"_"#vlmul.MX#!if(sew_aware, "_E"#!shl(1, log2sew), "")) + (!cast(inst#"_"#kind#"_"#vlmul.MX#!if(isSEWAware, "_E"#!shl(1, log2sew), "")) result_reg_class:$rs3, (op1_type op1_reg_class:$rs1), op2_kind:$rs2, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 93020d3fc5aec..c69d888517521 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -955,7 +955,7 @@ multiclass VPatBinaryV_VV_NoMask; + isSEWAware = isSEWAware>; } multiclass VPatBinaryV_VI_NoMask