diff --git a/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt index 97a6f886d114e..d3f16e5042c3a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt @@ -12,6 +12,8 @@ add_llvm_component_library(LLVMMipsDesc MipsNaClELFStreamer.cpp MipsOptionRecord.cpp MipsTargetStreamer.cpp + MipsWinCOFFObjectWriter.cpp + MipsWinCOFFStreamer.cpp LINK_COMPONENTS CodeGenTypes diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index e41b8797f9ce6..6001d9d51d16a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -593,10 +593,30 @@ bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { return false; } +namespace { + +class WindowsMipsAsmBackend : public MipsAsmBackend { +public: + WindowsMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, + const MCSubtargetInfo &STI) + : MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), false) {} + + std::unique_ptr + createObjectTargetWriter() const override { + return createMipsWinCOFFObjectWriter(); + } +}; + +} // end anonymous namespace + MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { + const Triple &TheTriple = STI.getTargetTriple(); + if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) + return new WindowsMipsAsmBackend(T, MRI, STI); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options); return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index 074a58cadb556..fa09a14b3e238 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -51,3 +51,14 @@ MipsELFMCAsmInfo::MipsELFMCAsmInfo(const Triple &TheTriple, DwarfRegNumForCFI = true; HasMipsExpressions = true; } + +void MipsCOFFMCAsmInfo::anchor() {} + +MipsCOFFMCAsmInfo::MipsCOFFMCAsmInfo() { + HasSingleParameterDotFile = true; + WinEHEncodingType = WinEH::EncodingType::Itanium; + + ExceptionsType = ExceptionHandling::WinEH; + + AllowAtInName = true; +} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h index b52ed12d3a0e7..3a2895a79f9c7 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H +#include "llvm/MC/MCAsmInfoCOFF.h" #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { @@ -26,6 +27,13 @@ class MipsELFMCAsmInfo : public MCAsmInfoELF { const MCTargetOptions &Options); }; +class MipsCOFFMCAsmInfo : public MCAsmInfoGNUCOFF { + void anchor() override; + +public: + explicit MipsCOFFMCAsmInfo(); +}; + } // namespace llvm #endif diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 3b655363ce26f..6558988175829 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -44,6 +44,13 @@ using namespace llvm; #define GET_REGINFO_MC_DESC #include "MipsGenRegisterInfo.inc" +namespace { +class MipsWinCOFFTargetStreamer : public MipsTargetStreamer { +public: + MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {} +}; +} // end namespace + /// Select the Mips CPU for the given triple and cpu name. StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { if (CPU.empty() || CPU == "generic") { @@ -83,7 +90,12 @@ static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { - MCAsmInfo *MAI = new MipsELFMCAsmInfo(TT, Options); + MCAsmInfo *MAI; + + if (TT.isOSWindows()) + MAI = new MipsCOFFMCAsmInfo(); + else + MAI = new MipsELFMCAsmInfo(TT, Options); unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); @@ -126,6 +138,8 @@ static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { static MCTargetStreamer * createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + if (STI.getTargetTriple().isOSBinFormatCOFF()) + return new MipsWinCOFFTargetStreamer(S); return new MipsTargetELFStreamer(S, STI); } @@ -185,6 +199,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { TargetRegistry::RegisterNullTargetStreamer(*T, createMipsNullTargetStreamer); + TargetRegistry::RegisterCOFFStreamer(*T, createMipsWinCOFFStreamer); + // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index d51f3b9abcfd1..c5293b03b0ac5 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -23,7 +23,9 @@ class MCCodeEmitter; class MCContext; class MCInstrInfo; class MCObjectTargetWriter; +class MCObjectWriter; class MCRegisterInfo; +class MCStreamer; class MCSubtargetInfo; class MCTargetOptions; class StringRef; @@ -39,8 +41,20 @@ MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options); +/// Construct an MIPS Windows COFF machine code streamer which will generate +/// PE/COFF format object files. +/// +/// Takes ownership of \p AB and \p CE. +MCStreamer *createMipsWinCOFFStreamer(MCContext &C, + std::unique_ptr &&AB, + std::unique_ptr &&OW, + std::unique_ptr &&CE); + +/// Construct a Mips ELF object writer. std::unique_ptr createMipsELFObjectWriter(const Triple &TT, bool IsN32); +/// Construct a Mips Win COFF object writer. +std::unique_ptr createMipsWinCOFFObjectWriter(); namespace MIPS_MC { StringRef selectMipsCPU(const Triple &TT, StringRef CPU); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp new file mode 100644 index 0000000000000..94187c71ba70d --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp @@ -0,0 +1,57 @@ +//===- MipsWinCOFFObjectWriter.cpp------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#include "MCTargetDesc/MipsFixupKinds.h" +#include "MCTargetDesc/MipsMCTargetDesc.h" +#include "llvm/BinaryFormat/COFF.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCWinCOFFObjectWriter.h" + +using namespace llvm; + +namespace { + +class MipsWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter { +public: + MipsWinCOFFObjectWriter(); + + unsigned getRelocType(MCContext &Ctx, const MCValue &Target, + const MCFixup &Fixup, bool IsCrossSection, + const MCAsmBackend &MAB) const override; +}; + +} // end anonymous namespace + +MipsWinCOFFObjectWriter::MipsWinCOFFObjectWriter() + : MCWinCOFFObjectTargetWriter(COFF::IMAGE_FILE_MACHINE_R4000) {} + +unsigned MipsWinCOFFObjectWriter::getRelocType(MCContext &Ctx, + const MCValue &Target, + const MCFixup &Fixup, + bool IsCrossSection, + const MCAsmBackend &MAB) const { + unsigned FixupKind = Fixup.getKind(); + + switch (FixupKind) { + case FK_Data_4: + return COFF::IMAGE_REL_MIPS_REFWORD; + case Mips::fixup_Mips_26: + return COFF::IMAGE_REL_MIPS_JMPADDR; + case Mips::fixup_Mips_HI16: + return COFF::IMAGE_REL_MIPS_REFHI; + case Mips::fixup_Mips_LO16: + return COFF::IMAGE_REL_MIPS_REFLO; + default: + Ctx.reportError(Fixup.getLoc(), "unsupported relocation type"); + return COFF::IMAGE_REL_MIPS_REFWORD; + } +} + +std::unique_ptr llvm::createMipsWinCOFFObjectWriter() { + return std::make_unique(); +} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFStreamer.cpp new file mode 100644 index 0000000000000..22bf2e1be203c --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFStreamer.cpp @@ -0,0 +1,33 @@ +//===- MipsWinCOFFStreamer.cpp-----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#include "MipsMCTargetDesc.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCWinCOFFStreamer.h" + +using namespace llvm; + +namespace { +class MipsWinCOFFStreamer : public MCWinCOFFStreamer { +public: + MipsWinCOFFStreamer(MCContext &C, std::unique_ptr AB, + std::unique_ptr CE, + std::unique_ptr OW) + : MCWinCOFFStreamer(C, std::move(AB), std::move(CE), std::move(OW)) {} +}; +} // namespace + +MCStreamer *llvm::createMipsWinCOFFStreamer( + MCContext &C, std::unique_ptr &&AB, + std::unique_ptr &&OW, std::unique_ptr &&CE) { + return new MipsWinCOFFStreamer(C, std::move(AB), std::move(CE), + std::move(OW)); +} diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 2cd5098f608cd..30eb739212113 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -70,6 +70,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { } static std::unique_ptr createTLOF(const Triple &TT) { + if (TT.isOSBinFormatCOFF()) + return std::make_unique(); return std::make_unique(); } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll index 203202e0bd053..b5bdf840facf4 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll index 84cdd9456dc82..3462f1d2b9d46 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/addressing-mode.ll b/llvm/test/CodeGen/Mips/addressing-mode.ll index 74543f6cdb9fd..9d4363765c96a 100644 --- a/llvm/test/CodeGen/Mips/addressing-mode.ll +++ b/llvm/test/CodeGen/Mips/addressing-mode.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll index 62af633ea8957..f3308c4b6ad12 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 define i64 @test_max(ptr nocapture %ptr, i64 signext %val) { ; MIPS-LABEL: test_max: diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll index a10db052a4ff2..85bf6d02c7d8f 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll @@ -1,17 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -mtriple=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -mtriple=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM -; RUN: llc -mtriple=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 -; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL -; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 -; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL -; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 -; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 -; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL -; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) { ; MIPS-LABEL: test_max_32: diff --git a/llvm/test/CodeGen/Mips/brconeq.ll b/llvm/test/CodeGen/Mips/brconeq.ll index 468456effd477..7c23db8d96fc4 100644 --- a/llvm/test/CodeGen/Mips/brconeq.ll +++ b/llvm/test/CodeGen/Mips/brconeq.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqk.ll b/llvm/test/CodeGen/Mips/brconeqk.ll index d0c6656cb52e1..98d8b07bc8091 100644 --- a/llvm/test/CodeGen/Mips/brconeqk.ll +++ b/llvm/test/CodeGen/Mips/brconeqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqz.ll b/llvm/test/CodeGen/Mips/brconeqz.ll index c99c5a2e47d6e..fbc50a7701b35 100644 --- a/llvm/test/CodeGen/Mips/brconeqz.ll +++ b/llvm/test/CodeGen/Mips/brconeqz.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconge.ll b/llvm/test/CodeGen/Mips/brconge.ll index 44d7556b5577b..4e91f4624aa6d 100644 --- a/llvm/test/CodeGen/Mips/brconge.ll +++ b/llvm/test/CodeGen/Mips/brconge.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brcongt.ll b/llvm/test/CodeGen/Mips/brcongt.ll index c332820a83a8c..1152167f3a8ab 100644 --- a/llvm/test/CodeGen/Mips/brcongt.ll +++ b/llvm/test/CodeGen/Mips/brcongt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconle.ll b/llvm/test/CodeGen/Mips/brconle.ll index e695f4be18f1f..d68362f253a3a 100644 --- a/llvm/test/CodeGen/Mips/brconle.ll +++ b/llvm/test/CodeGen/Mips/brconle.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 -5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll index 6ae8c64b4f09c..522db0d9e2da5 100644 --- a/llvm/test/CodeGen/Mips/brconlt.ll +++ b/llvm/test/CodeGen/Mips/brconlt.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -mtriple=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips-elf -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconne.ll b/llvm/test/CodeGen/Mips/brconne.ll index 40a15cdefba73..e673727def7d9 100644 --- a/llvm/test/CodeGen/Mips/brconne.ll +++ b/llvm/test/CodeGen/Mips/brconne.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 5, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnek.ll b/llvm/test/CodeGen/Mips/brconnek.ll index 3b74c777e0c2e..f963be59c12f4 100644 --- a/llvm/test/CodeGen/Mips/brconnek.ll +++ b/llvm/test/CodeGen/Mips/brconnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnez.ll b/llvm/test/CodeGen/Mips/brconnez.ll index e153964fab40a..15ba7c16cb3dd 100644 --- a/llvm/test/CodeGen/Mips/brconnez.ll +++ b/llvm/test/CodeGen/Mips/brconnez.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 0, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll index 42f9d1890cc37..c95fe09de20e7 100644 --- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips-elf < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the memory layout for all ABI's and byte orders as specified by section ; 4 of MD00305 (MIPS ABIs Described). diff --git a/llvm/test/CodeGen/Mips/cfi_offset.ll b/llvm/test/CodeGen/Mips/cfi_offset.ll index f687212558843..e55924e2f5353 100644 --- a/llvm/test/CodeGen/Mips/cfi_offset.ll +++ b/llvm/test/CodeGen/Mips/cfi_offset.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -mtriple=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -mtriple=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -mtriple=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL @var = global double 0.0 diff --git a/llvm/test/CodeGen/Mips/dins.ll b/llvm/test/CodeGen/Mips/dins.ll index aecc06bc7203a..cdb8f419eb2be 100644 --- a/llvm/test/CodeGen/Mips/dins.ll +++ b/llvm/test/CodeGen/Mips/dins.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 -; RUN: llc -O2 -verify-machineinstrs -mtriple=mips -mcpu=mips32r2 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mcpu=mips32r2 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS32R2 -; RUN: llc -O2 -verify-machineinstrs -mtriple=mips -mattr=mips16 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mattr=mips16 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS16 -; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 ; #include diff --git a/llvm/test/CodeGen/Mips/dsp-r1.ll b/llvm/test/CodeGen/Mips/dsp-r1.ll index 2b5a0d25aed7f..7a661d6c70514 100644 --- a/llvm/test/CodeGen/Mips/dsp-r1.ll +++ b/llvm/test/CodeGen/Mips/dsp-r1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ ; RUN: FileCheck %s define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll index 50c8b1dca9901..0c60c47310952 100644 --- a/llvm/test/CodeGen/Mips/eh-return32.ll +++ b/llvm/test/CodeGen/Mips/eh-return32.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i32(i32, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll index 3a2fb2a4868d8..f5a547a3b608c 100644 --- a/llvm/test/CodeGen/Mips/eh-return64.ll +++ b/llvm/test/CodeGen/Mips/eh-return64.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -mtriple=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i64(i64, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/emit-big-cst.ll b/llvm/test/CodeGen/Mips/emit-big-cst.ll index 5a8852e38e3df..5171e22abab6f 100644 --- a/llvm/test/CodeGen/Mips/emit-big-cst.ll +++ b/llvm/test/CodeGen/Mips/emit-big-cst.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=BE -; RUN: llc -mtriple=mipsel < %s | FileCheck %s --check-prefix=LE +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s --check-prefix=BE +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s --check-prefix=LE ; Check assembly printing of odd constants. ; BE-LABEL: bigCst: diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll index bdc676713ad7b..d0fa4058e41e7 100644 --- a/llvm/test/CodeGen/Mips/ex2.ll +++ b/llvm/test/CodeGen/Mips/ex2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @_ZTIPKc = external constant ptr diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index 9f7baca881fc0..7193a426ab0d2 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR -; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll index 7e92e3e7de6da..8f73cb33c4b68 100644 --- a/llvm/test/CodeGen/Mips/frame-address.ll +++ b/llvm/test/CodeGen/Mips/frame-address.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s declare ptr @llvm.frameaddress(i32) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/jumptable_labels.ll b/llvm/test/CodeGen/Mips/jumptable_labels.ll index fa8180847885a..075b57e08d35e 100644 --- a/llvm/test/CodeGen/Mips/jumptable_labels.ll +++ b/llvm/test/CodeGen/Mips/jumptable_labels.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -mtriple=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 -; RUN: llc -mtriple=mips64 < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -mtriple=mips64-elf -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 +; RUN: llc -mtriple=mips64-elf < %s | FileCheck %s -check-prefix=N64 ; We only use the '$' prefix on O32. The others use the ELF convention. ; O32: $JTI0_0 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll index 6a08b29458485..f6b3b96aaa0ce 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE4 -; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR3,MM32 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll index c5176669fec2e..c9490e59a623b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,16 +1,16 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C -; RUN: llc -mtriple=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(ptr %addr) { ; ALL-LABEL: br: diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll index 12728177380fc..20a06139a02b1 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M2,M2-M3 -; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-32 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M3,M2-M3 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-64 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R3 -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32R6 define signext i1 @tst_select_i1_i1(i1 signext %s, diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll index 3925b73527b43..0b7e51cbf7dc6 100644 --- a/llvm/test/CodeGen/Mips/load-store-left-right.ll +++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s -; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s -; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -mtriple=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s -; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s -; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s %struct.SLL = type { i64 } %struct.SI = type { i32 } diff --git a/llvm/test/CodeGen/Mips/mcount.ll b/llvm/test/CodeGen/Mips/mcount.ll index b45b59eedbc9c..41100e6cbeb6f 100644 --- a/llvm/test/CodeGen/Mips/mcount.ll +++ b/llvm/test/CodeGen/Mips/mcount.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=mips -verify-machineinstrs \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32 -; RUN: llc -mtriple=mips -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-PIC -; RUN: llc -mtriple=mips64 -verify-machineinstrs \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64 -; RUN: llc -mtriple=mips64 -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64-PIC -; RUN: llc -mtriple=mips -verify-machineinstrs -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM -; RUN: llc -mtriple=mips -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM-PIC ; Test that checks ABI for _mcount calls. diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll index ca4d6856f87f1..663fb078ecb82 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s define void @f1(ptr %p) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/Mips/mips64directive.ll b/llvm/test/CodeGen/Mips/mips64directive.ll index 3d5a32f43982e..1434be0b6bf64 100644 --- a/llvm/test/CodeGen/Mips/mips64directive.ll +++ b/llvm/test/CodeGen/Mips/mips64directive.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 | FileCheck %s @gl = global i64 1250999896321, align 8 diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index 32a8734a4a170..f5cde12f4efca 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_nloc_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 615bbbad66ae0..23857db4b06b9 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll index 4a272e3fa17d1..61593f4690d9a 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_flog2_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll index cf2e604c2623f..7c8376746df4d 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll @@ -1,8 +1,8 @@ ; Test the MSA floating point conversion intrinsics (e.g. float->double) that ; are encoded with the 2RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> , align 16 @llvm_mips_fexupl_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll index b8593a7fb9368..2c7eb0f9ca102 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll index 9a5c9c14b47e8..3f4a766575408 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point to floating point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> , align 16 @llvm_mips_ffql_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index ec700da6f3c06..ee06361f370f2 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fclass_w_RES = global <4 x i32> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll index e3fdbecc6b7eb..dfb1458842e26 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point to fixed-point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> , align 16 @llvm_mips_ftq_h_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 69e862850a473..8f97d6b12e91b 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,11 +1,11 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not llc -mtriple=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not llc -mtriple=mips-elf -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll index f2c5ebb4a580a..fc1f0c1071e2c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-b.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll index 38cb386b5a99b..000ebf45c472d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-c.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceq_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll index 116e0ada6de7b..e46cfb0bedfdf 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-d.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'd' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll index e20064bff84e9..e9af30d8e73bd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-i.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'i' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll index 580ae4b41c621..7a318ceed832d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-m.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_max_a_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll index 455ebb4a31616..4b3862c8f12a2 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-p.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'p' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_pckev_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll index 6ea52fa856716..b86a560a29ffd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-s.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll index c71efdc0bb745..dacbf036f93c1 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-v.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'v' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_vshf_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll index d32af452c4fee..7e9de2152e0d0 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format and ; use the result as a third operand. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maddv_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll index 13546b6bf6fc3..a6e753ec0cf10 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -2,8 +2,8 @@ ; use the result as a third operand and results in wider elements than the ; operands had. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> , align 16 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index c8c7f0585412c..6b353e6cdcd03 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll index 36114fa9094b5..eed5bd2292561 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fadd_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll index 94c66715035a3..a53e3d58fa72e 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fmadd_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll index 049042df39c11..41011024e09f7 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand and perform fixed-point operations. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll index b0ee043b8f371..58a890634eb44 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point conversion intrinsics that are encoded with the ; 3RF instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> , align 16 @llvm_mips_fexdo_h_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 49e31465d8477..d628d5ab1bbbe 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; take an integer as an operand. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll index 7c1b2ffd100c3..137230aa6a6f7 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; produce an integer as a result. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fcaf_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fcaf_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll index fcae0713056e3..cc1588ce7de56 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction ; format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll index 84496e012908a..b97e0539fcf69 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: add_v4f32: diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index cc200eb915866..ea32774226510 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the BIT instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll index 12b118b0af53c..c34e89b196e8f 100644 --- a/llvm/test/CodeGen/Mips/msa/bitcast.ll +++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll @@ -1,7 +1,7 @@ ; Test the bitcast operation for big-endian and little-endian. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/compare.ll b/llvm/test/CodeGen/Mips/msa/compare.ll index 5027c45ecf52e..351f0f1f79a34 100644 --- a/llvm/test/CodeGen/Mips/msa/compare.ll +++ b/llvm/test/CodeGen/Mips/msa/compare.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: ceq_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll index 396d8c421d123..2656cb839768c 100644 --- a/llvm/test/CodeGen/Mips/msa/compare_float.ll +++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index 232f09fc3a668..27d2faa8e66f1 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll index dab5e0c1b93a3..dd8afa61e3db5 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll index b5b22fd8ee0c9..23acdc0b9bbf8 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,13 +1,13 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll index 9e13d52f28bc2..ed368815838bc 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_move.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll @@ -1,8 +1,8 @@ ; Test the MSA move intrinsics (which are encoded with the ELM instruction ; format). -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_move_vb_ARG1 = global <16 x i8> , align 16 @llvm_mips_move_vb_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index 330da8b04469e..8195595c62d14 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sldi_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/endian.ll b/llvm/test/CodeGen/Mips/msa/endian.ll index e7ed31d145270..c9e63403d6ee3 100644 --- a/llvm/test/CodeGen/Mips/msa/endian.ll +++ b/llvm/test/CodeGen/Mips/msa/endian.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s @v16i8 = global <16 x i8> @v8i16 = global <8 x i16> diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll index 4d7fc78595f57..f6d46b1866837 100644 --- a/llvm/test/CodeGen/Mips/msa/frameindex.ll +++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s define void @loadstore_v16i8_near() nounwind { ; CHECK: loadstore_v16i8_near: diff --git a/llvm/test/CodeGen/Mips/msa/i10.ll b/llvm/test/CodeGen/Mips/msa/i10.ll index a9f95df0d0e83..2698c91308f71 100644 --- a/llvm/test/CodeGen/Mips/msa/i10.ll +++ b/llvm/test/CodeGen/Mips/msa/i10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I10 instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll index b46d0afcb8304..2e551a6a04c34 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-a.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_addvi_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll index fb4a21bf4ed3c..976dfcf9c2700 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-c.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceqi_b_RES1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll index 60ed8b7c86165..c1729a7ba0de6 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-m.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maxi_s_b_RES1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll index 66cb32eb88246..b54247ea07074 100644 --- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format and ; are loads or stores. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ld_b_ARG = global <16 x i8> , align 16 @llvm_mips_ld_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll index e4c1affc701fb..b286574079da6 100644 --- a/llvm/test/CodeGen/Mips/msa/i8.ll +++ b/llvm/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_andi_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll index cd52077173dc3..313b51ee31f4c 100644 --- a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll +++ b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=mipsel-elf -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s ; Test that checks if spill for ldi can be avoided and instruction will be ; rematerialized. diff --git a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll index 3f35a5be849ec..dbbd0fdfaf898 100644 --- a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll +++ b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ashr_v4i32(ptr %c) nounwind { ; CHECK-LABEL: ashr_v4i32: diff --git a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll index 2636f37a06ae6..79fb1b04da5f7 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll @@ -1,13 +1,13 @@ ; Test whether the following functions, with vectors featuring negative or values larger than the element ; bit size have their results of operations generated correctly when placed into constant pools -; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s -; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s @llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/special.ll b/llvm/test/CodeGen/Mips/msa/special.ll index df19d94eeed32..f70d9db348411 100644 --- a/llvm/test/CodeGen/Mips/msa/special.ll +++ b/llvm/test/CodeGen/Mips/msa/special.ll @@ -1,12 +1,12 @@ ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 -; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll index 51759f917a32c..5b00f3cad12cf 100644 --- a/llvm/test/CodeGen/Mips/msa/spill.ll +++ b/llvm/test/CodeGen/Mips/msa/spill.ll @@ -1,8 +1,8 @@ ; Test that the correct instruction is chosen for spill and reload by trying ; to have 33 live MSA registers simultaneously -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define i32 @test_i8(ptr %p0, ptr %q1) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll index 8f3a822704fea..21c550bc75428 100644 --- a/llvm/test/CodeGen/Mips/msa/vec.ll +++ b/llvm/test/CodeGen/Mips/msa/vec.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/vecs10.ll b/llvm/test/CodeGen/Mips/msa/vecs10.ll index 12da397a5d018..9d720f5f318cf 100644 --- a/llvm/test/CodeGen/Mips/msa/vecs10.ll +++ b/llvm/test/CodeGen/Mips/msa/vecs10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. -; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_v_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll index 09a35e05cb454..e6c375a0d9c30 100644 --- a/llvm/test/CodeGen/Mips/octeon.ll +++ b/llvm/test/CodeGen/Mips/octeon.ll @@ -1,6 +1,6 @@ -; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON -; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 -; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC define i64 @addi64(i64 %a, i64 %b) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/prevent-hoisting.ll b/llvm/test/CodeGen/Mips/prevent-hoisting.ll index 05b7e964c9ae0..3d659746ddb9d 100644 --- a/llvm/test/CodeGen/Mips/prevent-hoisting.ll +++ b/llvm/test/CodeGen/Mips/prevent-hoisting.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -O3 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -O3 -relocation-model=pic < %s | FileCheck %s ; MIPS direct branches implicitly define register $at. This test makes sure that diff --git a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll index 6520bcdc0622a..939d192ba28e5 100644 --- a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll index 9c3089d56ae32..7524bf2408673 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll index 1e32d9f2be1f6..792168e567dbf 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/seleq.ll b/llvm/test/CodeGen/Mips/seleq.ll index fcf12202b40ca..579c9c140a6b3 100644 --- a/llvm/test/CodeGen/Mips/seleq.ll +++ b/llvm/test/CodeGen/Mips/seleq.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/seleqk.ll b/llvm/test/CodeGen/Mips/seleqk.ll index 6292494671717..73a5967ae4aa2 100644 --- a/llvm/test/CodeGen/Mips/seleqk.ll +++ b/llvm/test/CodeGen/Mips/seleqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgek.ll b/llvm/test/CodeGen/Mips/selgek.ll index 9c9e77ae236a7..a9de8b20dfe39 100644 --- a/llvm/test/CodeGen/Mips/selgek.ll +++ b/llvm/test/CodeGen/Mips/selgek.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgt.ll b/llvm/test/CodeGen/Mips/selgt.ll index a59c89f875173..47648490a5e3f 100644 --- a/llvm/test/CodeGen/Mips/selgt.ll +++ b/llvm/test/CodeGen/Mips/selgt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selle.ll b/llvm/test/CodeGen/Mips/selle.ll index 59fe279966183..c7a321d4aa04d 100644 --- a/llvm/test/CodeGen/Mips/selle.ll +++ b/llvm/test/CodeGen/Mips/selle.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selltk.ll b/llvm/test/CodeGen/Mips/selltk.ll index 2661ea1dead26..dccee12a51024 100644 --- a/llvm/test/CodeGen/Mips/selltk.ll +++ b/llvm/test/CodeGen/Mips/selltk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selne.ll b/llvm/test/CodeGen/Mips/selne.ll index 0d117c4d76601..ff4cd116441c0 100644 --- a/llvm/test/CodeGen/Mips/selne.ll +++ b/llvm/test/CodeGen/Mips/selne.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selnek.ll b/llvm/test/CodeGen/Mips/selnek.ll index ecc68842cc623..f21693aeff0c7 100644 --- a/llvm/test/CodeGen/Mips/selnek.ll +++ b/llvm/test/CodeGen/Mips/selnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selpat.ll b/llvm/test/CodeGen/Mips/selpat.ll index ad263bb41295b..dafe40e763636 100644 --- a/llvm/test/CodeGen/Mips/selpat.ll +++ b/llvm/test/CodeGen/Mips/selpat.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll index 030c640522752..912998ab9d038 100644 --- a/llvm/test/CodeGen/Mips/unalignedload.ll +++ b/llvm/test/CodeGen/Mips/unalignedload.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } diff --git a/llvm/test/DebugInfo/Mips/tls.ll b/llvm/test/DebugInfo/Mips/tls.ll index 927966d514078..5a00d6b757c36 100644 --- a/llvm/test/DebugInfo/Mips/tls.ll +++ b/llvm/test/DebugInfo/Mips/tls.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-WORD -; RUN: llc -O0 -mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=CHECK-DWORD +; RUN: llc -O0 -mtriple=mips-elf -mcpu=mips32r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-WORD +; RUN: llc -O0 -mtriple=mips64-elf -mcpu=mips64r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-DWORD @x = thread_local global i32 5, align 4, !dbg !0 diff --git a/llvm/test/MC/Mips/coff-basic.ll b/llvm/test/MC/Mips/coff-basic.ll new file mode 100644 index 0000000000000..4c25cd659c5c7 --- /dev/null +++ b/llvm/test/MC/Mips/coff-basic.ll @@ -0,0 +1,7 @@ +; RUN: llc -mtriple mipsel-windows -filetype=obj < %s | obj2yaml | FileCheck %s + +define i32 @foo() { + ret i32 0 +} + +; CHECK: Machine: IMAGE_FILE_MACHINE_R4000 diff --git a/llvm/test/MC/Mips/coff-relocs.ll b/llvm/test/MC/Mips/coff-relocs.ll new file mode 100644 index 0000000000000..1d8b3f192d7af --- /dev/null +++ b/llvm/test/MC/Mips/coff-relocs.ll @@ -0,0 +1,42 @@ +; RUN: llc -mtriple mipsel-windows -filetype=obj < %s | obj2yaml | FileCheck %s + +; CHECK: Machine: IMAGE_FILE_MACHINE_R4000 + + + +; CHECK: - Name: .text +; CHECK: Relocations: + +declare void @bar() +define i32 @foo_jmp() { + call i32 @bar() +; CHECK: - VirtualAddress: 8 +; CHECK: SymbolName: bar +; CHECK: Type: IMAGE_REL_MIPS_JMPADDR + ret i32 0 +} + +@var = external global i32 +define i32 @foo_var() { + %1 = load i32, i32* @var +; CHECK: - VirtualAddress: 32 +; CHECK: SymbolName: var +; CHECK: Type: IMAGE_REL_MIPS_REFHI +; CHECK: - VirtualAddress: 40 +; CHECK: SymbolName: var +; CHECK: Type: IMAGE_REL_MIPS_REFLO + ret i32 %1 +} + + + +; CHECK: - Name: .data +; CHECK: Relocations: + +%struct._PTR = type { ptr } + +@var1 = internal global %struct._PTR { ptr @var2 } +@var2 = external global i32 +; CHECK: - VirtualAddress: 0 +; CHECK: SymbolName: var2 +; CHECK: Type: IMAGE_REL_MIPS_REFWORD