From 0de8d2b5c89b090abe084ddd7d8bb13d6b659b5f Mon Sep 17 00:00:00 2001 From: Maryam Moghadas Date: Sat, 2 Nov 2024 10:05:05 -0400 Subject: [PATCH] Revert "[PowerPC] Add custom lowering for ssubo (#111748)" This reverts commit 8a0cb9ac869334fd6c6bd6aad8408623a7ccd7f6. --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 37 --------------------- llvm/lib/Target/PowerPC/PPCISelLowering.h | 1 - llvm/test/CodeGen/PowerPC/saddo-ssubo.ll | 11 +++--- 3 files changed, 6 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d8f3095ed7fb6..ab31898e262e7 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -200,11 +200,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom); - // On P10, the default lowering generates better code using the - // setbc instruction. - if (!Subtarget.hasP10Vector() && isPPC64) - setOperationAction(ISD::SSUBO, MVT::i32, Custom); - // Match BITREVERSE to customized fast code sequence in the td file. setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); @@ -12021,36 +12016,6 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const { return Res; } -SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const { - - SDLoc dl(Op); - - SDValue LHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(0)); - SDValue RHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(1)); - - SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i64, LHS64, RHS64); - - SDValue Extsw = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i64, Sub, - DAG.getValueType(MVT::i32)); - - SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i64, Extsw, Sub); - - SDValue Addic = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(MVT::i64, MVT::Glue), - Xor, DAG.getConstant(-1, dl, MVT::i64)); - - SDValue Overflow = - DAG.getNode(ISD::SUBE, dl, DAG.getVTList(MVT::i64, MVT::Glue), Xor, Addic, - Addic.getValue(1)); - - SDValue OverflowTrunc = - DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow); - SDValue SubTrunc = - (Sub->getValueType(0) != Op.getNode()->getValueType(0)) - ? DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(0), Sub) - : Sub; - return DAG.getMergeValues({SubTrunc, OverflowTrunc}, dl); -} - /// LowerOperation - Provide custom lowering hooks for some operations. /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { @@ -12073,8 +12038,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); - case ISD::SSUBO: - return LowerSSUBO(Op, DAG); case ISD::INLINEASM: case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index dde45e4cf6f4a..0adbad8684597 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1279,7 +1279,6 @@ namespace llvm { SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll index 7147257d27c4b..fd5f26ba35742 100644 --- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll +++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll @@ -129,11 +129,12 @@ entry: define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: test_ssubo_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sub 3, 3, 4 -; CHECK-NEXT: extsw 4, 3 -; CHECK-NEXT: xor 3, 4, 3 -; CHECK-NEXT: addic 4, 3, -1 -; CHECK-NEXT: subfe 3, 4, 3 +; CHECK-NEXT: sub 5, 3, 4 +; CHECK-NEXT: cmpwi 1, 4, 0 +; CHECK-NEXT: cmpw 5, 3 +; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: creqv 20, 5, 0 +; CHECK-NEXT: isel 3, 0, 3, 20 ; CHECK-NEXT: blr entry: %res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind