From 4a6f456bd8f20bb4731d541923bf49dae7a5e0dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sat, 2 Nov 2024 14:36:55 +0100 Subject: [PATCH] [CodeGen][Mips] Explicit ELF output file format for MIPS tests This will be required once MIPS architecture defaults to COFF files on Windows platforms. --- llvm/test/CodeGen/Mips/Fast-ISel/br1.ll | 4 +-- llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll | 2 +- llvm/test/CodeGen/Mips/addressing-mode.ll | 2 +- llvm/test/CodeGen/Mips/atomic-min-max-64.ll | 8 ++--- llvm/test/CodeGen/Mips/atomic-min-max.ll | 26 ++++++++-------- llvm/test/CodeGen/Mips/brconeq.ll | 2 +- llvm/test/CodeGen/Mips/brconeqk.ll | 2 +- llvm/test/CodeGen/Mips/brconeqz.ll | 2 +- llvm/test/CodeGen/Mips/brconge.ll | 2 +- llvm/test/CodeGen/Mips/brcongt.ll | 2 +- llvm/test/CodeGen/Mips/brconle.ll | 2 +- llvm/test/CodeGen/Mips/brconlt.ll | 4 +-- llvm/test/CodeGen/Mips/brconne.ll | 2 +- llvm/test/CodeGen/Mips/brconnek.ll | 2 +- llvm/test/CodeGen/Mips/brconnez.ll | 2 +- llvm/test/CodeGen/Mips/cconv/memory-layout.ll | 16 +++++----- llvm/test/CodeGen/Mips/cfi_offset.ll | 12 ++++---- llvm/test/CodeGen/Mips/dins.ll | 8 ++--- llvm/test/CodeGen/Mips/dsp-r1.ll | 2 +- llvm/test/CodeGen/Mips/eh-return32.ll | 6 ++-- llvm/test/CodeGen/Mips/eh-return64.ll | 8 ++--- llvm/test/CodeGen/Mips/emit-big-cst.ll | 4 +-- llvm/test/CodeGen/Mips/ex2.ll | 2 +- llvm/test/CodeGen/Mips/fpbr.ll | 12 ++++---- llvm/test/CodeGen/Mips/frame-address.ll | 2 +- llvm/test/CodeGen/Mips/jumptable_labels.ll | 6 ++-- llvm/test/CodeGen/Mips/llvm-ir/add.ll | 30 +++++++++---------- llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll | 22 +++++++------- llvm/test/CodeGen/Mips/llvm-ir/select-int.ll | 30 +++++++++---------- .../CodeGen/Mips/load-store-left-right.ll | 28 ++++++++--------- llvm/test/CodeGen/Mips/mcount.ll | 12 ++++---- .../micromips-lbu16-lhu16-sb16-sh16.ll | 2 +- llvm/test/CodeGen/Mips/mips64directive.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2r.ll | 4 +-- .../test/CodeGen/Mips/msa/2r_vector_scalar.ll | 8 ++--- llvm/test/CodeGen/Mips/msa/2rf.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2rf_exup.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2rf_float_int.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2rf_fq.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2rf_int_float.ll | 4 +-- llvm/test/CodeGen/Mips/msa/2rf_tq.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-a.ll | 6 ++-- llvm/test/CodeGen/Mips/msa/3r-b.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-c.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-d.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-i.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-m.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-p.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-s.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r-v.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r_4r.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3r_splat.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_4rf.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_exdo.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_float_int.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_int_float.ll | 4 +-- llvm/test/CodeGen/Mips/msa/3rf_q.ll | 4 +-- .../test/CodeGen/Mips/msa/arithmetic_float.ll | 4 +-- llvm/test/CodeGen/Mips/msa/bit.ll | 4 +-- llvm/test/CodeGen/Mips/msa/bitcast.ll | 4 +-- llvm/test/CodeGen/Mips/msa/compare.ll | 4 +-- llvm/test/CodeGen/Mips/msa/compare_float.ll | 4 +-- llvm/test/CodeGen/Mips/msa/elm_copy.ll | 8 ++--- llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll | 4 +-- llvm/test/CodeGen/Mips/msa/elm_insv.ll | 8 ++--- llvm/test/CodeGen/Mips/msa/elm_move.ll | 4 +-- llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll | 4 +-- llvm/test/CodeGen/Mips/msa/endian.ll | 4 +-- llvm/test/CodeGen/Mips/msa/frameindex.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i10.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i5-a.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i5-c.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i5-m.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i5_ld_st.ll | 4 +-- llvm/test/CodeGen/Mips/msa/i8.ll | 4 +-- llvm/test/CodeGen/Mips/msa/remat-ldi.ll | 2 +- .../test/CodeGen/Mips/msa/shift-dagcombine.ll | 2 +- .../CodeGen/Mips/msa/shift_constant_pool.ll | 8 ++--- llvm/test/CodeGen/Mips/msa/special.ll | 8 ++--- llvm/test/CodeGen/Mips/msa/spill.ll | 4 +-- llvm/test/CodeGen/Mips/msa/vec.ll | 4 +-- llvm/test/CodeGen/Mips/msa/vecs10.ll | 4 +-- llvm/test/CodeGen/Mips/octeon.ll | 6 ++-- llvm/test/CodeGen/Mips/prevent-hoisting.ll | 2 +- llvm/test/CodeGen/Mips/selTBteqzCmpi.ll | 2 +- llvm/test/CodeGen/Mips/selTBtnezCmpi.ll | 2 +- llvm/test/CodeGen/Mips/selTBtnezSlti.ll | 2 +- llvm/test/CodeGen/Mips/seleq.ll | 2 +- llvm/test/CodeGen/Mips/seleqk.ll | 2 +- llvm/test/CodeGen/Mips/selgek.ll | 2 +- llvm/test/CodeGen/Mips/selgt.ll | 2 +- llvm/test/CodeGen/Mips/selle.ll | 2 +- llvm/test/CodeGen/Mips/selltk.ll | 2 +- llvm/test/CodeGen/Mips/selne.ll | 2 +- llvm/test/CodeGen/Mips/selnek.ll | 2 +- llvm/test/CodeGen/Mips/selpat.ll | 2 +- llvm/test/CodeGen/Mips/unalignedload.ll | 12 ++++---- llvm/test/DebugInfo/Mips/tls.ll | 4 +-- 101 files changed, 272 insertions(+), 272 deletions(-) diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll index 2f0f1a04a5588..b5bdf840facf4 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll index 37e49c2e8a428..3462f1d2b9d46 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/addressing-mode.ll b/llvm/test/CodeGen/Mips/addressing-mode.ll index bd8daf45be2c4..9d4363765c96a 100644 --- a/llvm/test/CodeGen/Mips/addressing-mode.ll +++ b/llvm/test/CodeGen/Mips/addressing-mode.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll index 5273f499cedec..f3308c4b6ad12 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 define i64 @test_max(ptr nocapture %ptr, i64 signext %val) { ; MIPS-LABEL: test_max: diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll index 3d3225509d1ae..85bf6d02c7d8f 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll @@ -1,17 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 -; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL -; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 -; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL -; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 -; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 -; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL -; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) { ; MIPS-LABEL: test_max_32: diff --git a/llvm/test/CodeGen/Mips/brconeq.ll b/llvm/test/CodeGen/Mips/brconeq.ll index ba7dc0f8540e6..7c23db8d96fc4 100644 --- a/llvm/test/CodeGen/Mips/brconeq.ll +++ b/llvm/test/CodeGen/Mips/brconeq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqk.ll b/llvm/test/CodeGen/Mips/brconeqk.ll index 4ee2f772ff68e..98d8b07bc8091 100644 --- a/llvm/test/CodeGen/Mips/brconeqk.ll +++ b/llvm/test/CodeGen/Mips/brconeqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqz.ll b/llvm/test/CodeGen/Mips/brconeqz.ll index b8e7d1d12f978..fbc50a7701b35 100644 --- a/llvm/test/CodeGen/Mips/brconeqz.ll +++ b/llvm/test/CodeGen/Mips/brconeqz.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconge.ll b/llvm/test/CodeGen/Mips/brconge.ll index 38e3a7c3706f5..4e91f4624aa6d 100644 --- a/llvm/test/CodeGen/Mips/brconge.ll +++ b/llvm/test/CodeGen/Mips/brconge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brcongt.ll b/llvm/test/CodeGen/Mips/brcongt.ll index 3231811588fc1..1152167f3a8ab 100644 --- a/llvm/test/CodeGen/Mips/brcongt.ll +++ b/llvm/test/CodeGen/Mips/brcongt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconle.ll b/llvm/test/CodeGen/Mips/brconle.ll index e0ade5df23775..d68362f253a3a 100644 --- a/llvm/test/CodeGen/Mips/brconle.ll +++ b/llvm/test/CodeGen/Mips/brconle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 -5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll index f3dbb9607eaff..522db0d9e2da5 100644 --- a/llvm/test/CodeGen/Mips/brconlt.ll +++ b/llvm/test/CodeGen/Mips/brconlt.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips-elf -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconne.ll b/llvm/test/CodeGen/Mips/brconne.ll index 5c3a0ef343291..e673727def7d9 100644 --- a/llvm/test/CodeGen/Mips/brconne.ll +++ b/llvm/test/CodeGen/Mips/brconne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 5, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnek.ll b/llvm/test/CodeGen/Mips/brconnek.ll index 30c32825da52e..f963be59c12f4 100644 --- a/llvm/test/CodeGen/Mips/brconnek.ll +++ b/llvm/test/CodeGen/Mips/brconnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnez.ll b/llvm/test/CodeGen/Mips/brconnez.ll index 5f8b54e9cbb50..15ba7c16cb3dd 100644 --- a/llvm/test/CodeGen/Mips/brconnez.ll +++ b/llvm/test/CodeGen/Mips/brconnez.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 0, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll index dae4bfc226090..c95fe09de20e7 100644 --- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips-elf < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the memory layout for all ABI's and byte orders as specified by section ; 4 of MD00305 (MIPS ABIs Described). diff --git a/llvm/test/CodeGen/Mips/cfi_offset.ll b/llvm/test/CodeGen/Mips/cfi_offset.ll index 217adda59468a..e55924e2f5353 100644 --- a/llvm/test/CodeGen/Mips/cfi_offset.ll +++ b/llvm/test/CodeGen/Mips/cfi_offset.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL @var = global double 0.0 diff --git a/llvm/test/CodeGen/Mips/dins.ll b/llvm/test/CodeGen/Mips/dins.ll index 4deb7455a8012..cdb8f419eb2be 100644 --- a/llvm/test/CodeGen/Mips/dins.ll +++ b/llvm/test/CodeGen/Mips/dins.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 -; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mcpu=mips32r2 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS32R2 -; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mattr=mips16 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS16 -; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 ; #include diff --git a/llvm/test/CodeGen/Mips/dsp-r1.ll b/llvm/test/CodeGen/Mips/dsp-r1.ll index 0ec23b9d7fd77..7a661d6c70514 100644 --- a/llvm/test/CodeGen/Mips/dsp-r1.ll +++ b/llvm/test/CodeGen/Mips/dsp-r1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ ; RUN: FileCheck %s define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll index 983fc6f7788c7..0c60c47310952 100644 --- a/llvm/test/CodeGen/Mips/eh-return32.ll +++ b/llvm/test/CodeGen/Mips/eh-return32.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i32(i32, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll index 9ae2f00d46c1e..f5a547a3b608c 100644 --- a/llvm/test/CodeGen/Mips/eh-return64.ll +++ b/llvm/test/CodeGen/Mips/eh-return64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i64(i64, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/emit-big-cst.ll b/llvm/test/CodeGen/Mips/emit-big-cst.ll index cd0666cfd3fc2..5171e22abab6f 100644 --- a/llvm/test/CodeGen/Mips/emit-big-cst.ll +++ b/llvm/test/CodeGen/Mips/emit-big-cst.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=BE -; RUN: llc -march=mipsel < %s | FileCheck %s --check-prefix=LE +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s --check-prefix=BE +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s --check-prefix=LE ; Check assembly printing of odd constants. ; BE-LABEL: bigCst: diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll index 79aabfcbbfc43..d0fa4058e41e7 100644 --- a/llvm/test/CodeGen/Mips/ex2.ll +++ b/llvm/test/CodeGen/Mips/ex2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @_ZTIPKc = external constant ptr diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index 251c5392575b2..7193a426ab0d2 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll index 685d1fe1f4651..8f73cb33c4b68 100644 --- a/llvm/test/CodeGen/Mips/frame-address.ll +++ b/llvm/test/CodeGen/Mips/frame-address.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s declare ptr @llvm.frameaddress(i32) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/jumptable_labels.ll b/llvm/test/CodeGen/Mips/jumptable_labels.ll index 8ae22be9dd23a..075b57e08d35e 100644 --- a/llvm/test/CodeGen/Mips/jumptable_labels.ll +++ b/llvm/test/CodeGen/Mips/jumptable_labels.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 -; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -mtriple=mips64-elf -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 +; RUN: llc -mtriple=mips64-elf < %s | FileCheck %s -check-prefix=N64 ; We only use the '$' prefix on O32. The others use the ELF convention. ; O32: $JTI0_0 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll index 84c4bf677f945..f6b3b96aaa0ce 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE4 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR3,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll index aebeac9e5bd21..c9490e59a623b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,16 +1,16 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(ptr %addr) { ; ALL-LABEL: br: diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll index 8bf83c5c18ce7..20a06139a02b1 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M2,M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M3,M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32R6 define signext i1 @tst_select_i1_i1(i1 signext %s, diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll index 3c3110341df26..0b7e51cbf7dc6 100644 --- a/llvm/test/CodeGen/Mips/load-store-left-right.ll +++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s -; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s -; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s %struct.SLL = type { i64 } %struct.SI = type { i32 } diff --git a/llvm/test/CodeGen/Mips/mcount.ll b/llvm/test/CodeGen/Mips/mcount.ll index 8a129536d9769..41100e6cbeb6f 100644 --- a/llvm/test/CodeGen/Mips/mcount.ll +++ b/llvm/test/CodeGen/Mips/mcount.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -verify-machineinstrs \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32 -; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-PIC -; RUN: llc -march=mips64 -verify-machineinstrs \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64 -; RUN: llc -march=mips64 -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64-PIC -; RUN: llc -march=mips -verify-machineinstrs -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM -; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM-PIC ; Test that checks ABI for _mcount calls. diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll index 4cada64548f47..663fb078ecb82 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s define void @f1(ptr %p) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/Mips/mips64directive.ll b/llvm/test/CodeGen/Mips/mips64directive.ll index 6d6674496f7d0..1434be0b6bf64 100644 --- a/llvm/test/CodeGen/Mips/mips64directive.ll +++ b/llvm/test/CodeGen/Mips/mips64directive.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 | FileCheck %s @gl = global i64 1250999896321, align 8 diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index b7ea3fc11c6e3..f5cde12f4efca 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_nloc_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index f369a9ebca384..23857db4b06b9 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll index 6cdf5b7b8b423..61593f4690d9a 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_flog2_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll index f8bdf866c5f82..7c8376746df4d 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll @@ -1,8 +1,8 @@ ; Test the MSA floating point conversion intrinsics (e.g. float->double) that ; are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> , align 16 @llvm_mips_fexupl_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll index da83b7eb180b7..2c7eb0f9ca102 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll index 2d773bfda17c8..3f4a766575408 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point to floating point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> , align 16 @llvm_mips_ffql_w_RES = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index eeac8d4495716..ee06361f370f2 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fclass_w_RES = global <4 x i32> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll index 110da06777813..dfb1458842e26 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point to fixed-point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> , align 16 @llvm_mips_ftq_h_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 31646350b6802..8f97d6b12e91b 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,11 +1,11 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not llc -mtriple=mips-elf -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll index f824a6527d72d..fc1f0c1071e2c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-b.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll index 8af06b3f20bd4..000ebf45c472d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-c.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceq_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll index b40d2661ee6aa..e46cfb0bedfdf 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-d.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'd' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll index c06d79a975bf1..e9af30d8e73bd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-i.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'i' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll index 855ceb3dd8890..7a318ceed832d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-m.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_max_a_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll index 063da01c29db6..4b3862c8f12a2 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-p.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'p' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_pckev_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll index 6c673c543bf2f..b86a560a29ffd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-s.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll index 80828a07907cd..dacbf036f93c1 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-v.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'v' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_vshf_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll index abeaee682fb48..7e9de2152e0d0 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maddv_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll index 4b286a0e93cbd..a6e753ec0cf10 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -2,8 +2,8 @@ ; use the result as a third operand and results in wider elements than the ; operands had. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> , align 16 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index e8d9d23fa9b49..6b353e6cdcd03 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll index 9bae9ba530453..eed5bd2292561 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fadd_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll index 6142ada9fef91..a53e3d58fa72e 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fmadd_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll index f397644df3919..41011024e09f7 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand and perform fixed-point operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll index 70da349d0f13e..58a890634eb44 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point conversion intrinsics that are encoded with the ; 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> , align 16 @llvm_mips_fexdo_h_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 4c1328b49be56..d628d5ab1bbbe 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; take an integer as an operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll index 7e186beb32050..137230aa6a6f7 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; produce an integer as a result. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fcaf_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fcaf_w_ARG2 = global <4 x float> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll index 5e3358ccd063a..cc1588ce7de56 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction ; format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll index b2ce43171aeb1..b97e0539fcf69 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: add_v4f32: diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index 1b2012cec5f5a..ea32774226510 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the BIT instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll index 11c5a5fb42c79..c34e89b196e8f 100644 --- a/llvm/test/CodeGen/Mips/msa/bitcast.ll +++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll @@ -1,7 +1,7 @@ ; Test the bitcast operation for big-endian and little-endian. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/compare.ll b/llvm/test/CodeGen/Mips/msa/compare.ll index a3910bde8cd1c..351f0f1f79a34 100644 --- a/llvm/test/CodeGen/Mips/msa/compare.ll +++ b/llvm/test/CodeGen/Mips/msa/compare.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: ceq_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll index cd4924eca44cd..2656cb839768c 100644 --- a/llvm/test/CodeGen/Mips/msa/compare_float.ll +++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index 6e0ee2da0920f..27d2faa8e66f1 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll index 7d44620e25790..dd8afa61e3db5 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll index 6c00483cf6537..23acdc0b9bbf8 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,13 +1,13 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll index 4065fc753a55e..ed368815838bc 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_move.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll @@ -1,8 +1,8 @@ ; Test the MSA move intrinsics (which are encoded with the ELM instruction ; format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_move_vb_ARG1 = global <16 x i8> , align 16 @llvm_mips_move_vb_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index 548cdf394ac85..8195595c62d14 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sldi_b_ARG2 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/endian.ll b/llvm/test/CodeGen/Mips/msa/endian.ll index 63aa3f6e18724..c9e63403d6ee3 100644 --- a/llvm/test/CodeGen/Mips/msa/endian.ll +++ b/llvm/test/CodeGen/Mips/msa/endian.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s @v16i8 = global <16 x i8> @v8i16 = global <8 x i16> diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll index 1ee527bd88a4d..f6d46b1866837 100644 --- a/llvm/test/CodeGen/Mips/msa/frameindex.ll +++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s define void @loadstore_v16i8_near() nounwind { ; CHECK: loadstore_v16i8_near: diff --git a/llvm/test/CodeGen/Mips/msa/i10.ll b/llvm/test/CodeGen/Mips/msa/i10.ll index e130d6df4b90c..2698c91308f71 100644 --- a/llvm/test/CodeGen/Mips/msa/i10.ll +++ b/llvm/test/CodeGen/Mips/msa/i10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll index 7fd14da4b5f06..2e551a6a04c34 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-a.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_addvi_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll index 96f5e6286276a..976dfcf9c2700 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-c.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceqi_b_RES1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll index 74599185963a6..c1729a7ba0de6 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-m.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maxi_s_b_RES1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll index e55799cf17667..b54247ea07074 100644 --- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format and ; are loads or stores. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ld_b_ARG = global <16 x i8> , align 16 @llvm_mips_ld_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll index 89f5725c17357..b286574079da6 100644 --- a/llvm/test/CodeGen/Mips/msa/i8.ll +++ b/llvm/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_andi_b_RES = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll index 64f976c97a358..313b51ee31f4c 100644 --- a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll +++ b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -march=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=mipsel-elf -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s ; Test that checks if spill for ldi can be avoided and instruction will be ; rematerialized. diff --git a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll index 1f8572751c1a4..dbbd0fdfaf898 100644 --- a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll +++ b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ashr_v4i32(ptr %c) nounwind { ; CHECK-LABEL: ashr_v4i32: diff --git a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll index 9312a05f56960..79fb1b04da5f7 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll @@ -1,13 +1,13 @@ ; Test whether the following functions, with vectors featuring negative or values larger than the element ; bit size have their results of operations generated correctly when placed into constant pools -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s @llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/special.ll b/llvm/test/CodeGen/Mips/msa/special.ll index 3e392110cccfe..f70d9db348411 100644 --- a/llvm/test/CodeGen/Mips/msa/special.ll +++ b/llvm/test/CodeGen/Mips/msa/special.ll @@ -1,12 +1,12 @@ ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll index 29f02920b10c6..5b00f3cad12cf 100644 --- a/llvm/test/CodeGen/Mips/msa/spill.ll +++ b/llvm/test/CodeGen/Mips/msa/spill.ll @@ -1,8 +1,8 @@ ; Test that the correct instruction is chosen for spill and reload by trying ; to have 33 live MSA registers simultaneously -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define i32 @test_i8(ptr %p0, ptr %q1) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll index cc4eba6c95bf1..21c550bc75428 100644 --- a/llvm/test/CodeGen/Mips/msa/vec.ll +++ b/llvm/test/CodeGen/Mips/msa/vec.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/msa/vecs10.ll b/llvm/test/CodeGen/Mips/msa/vecs10.ll index ce61efc33f3a4..9d720f5f318cf 100644 --- a/llvm/test/CodeGen/Mips/msa/vecs10.ll +++ b/llvm/test/CodeGen/Mips/msa/vecs10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_v_ARG1 = global <16 x i8> , align 16 diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll index 11e93736f5cf0..e6c375a0d9c30 100644 --- a/llvm/test/CodeGen/Mips/octeon.ll +++ b/llvm/test/CodeGen/Mips/octeon.ll @@ -1,6 +1,6 @@ -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON -; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC define i64 @addi64(i64 %a, i64 %b) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/prevent-hoisting.ll b/llvm/test/CodeGen/Mips/prevent-hoisting.ll index e44b895689b49..3d659746ddb9d 100644 --- a/llvm/test/CodeGen/Mips/prevent-hoisting.ll +++ b/llvm/test/CodeGen/Mips/prevent-hoisting.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -O3 -relocation-model=pic < %s | FileCheck %s ; MIPS direct branches implicitly define register $at. This test makes sure that diff --git a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll index a81393b0b0807..939d192ba28e5 100644 --- a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll index e703e317a0fb8..7524bf2408673 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll index 132d5ed770207..792168e567dbf 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/seleq.ll b/llvm/test/CodeGen/Mips/seleq.ll index ecbeb2b51e3d7..579c9c140a6b3 100644 --- a/llvm/test/CodeGen/Mips/seleq.ll +++ b/llvm/test/CodeGen/Mips/seleq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/seleqk.ll b/llvm/test/CodeGen/Mips/seleqk.ll index 911c6f1996b67..73a5967ae4aa2 100644 --- a/llvm/test/CodeGen/Mips/seleqk.ll +++ b/llvm/test/CodeGen/Mips/seleqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgek.ll b/llvm/test/CodeGen/Mips/selgek.ll index a909bb543538b..a9de8b20dfe39 100644 --- a/llvm/test/CodeGen/Mips/selgek.ll +++ b/llvm/test/CodeGen/Mips/selgek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgt.ll b/llvm/test/CodeGen/Mips/selgt.ll index 30d7f8ff3a695..47648490a5e3f 100644 --- a/llvm/test/CodeGen/Mips/selgt.ll +++ b/llvm/test/CodeGen/Mips/selgt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selle.ll b/llvm/test/CodeGen/Mips/selle.ll index bccc3de56705e..c7a321d4aa04d 100644 --- a/llvm/test/CodeGen/Mips/selle.ll +++ b/llvm/test/CodeGen/Mips/selle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selltk.ll b/llvm/test/CodeGen/Mips/selltk.ll index b070c301b0199..dccee12a51024 100644 --- a/llvm/test/CodeGen/Mips/selltk.ll +++ b/llvm/test/CodeGen/Mips/selltk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selne.ll b/llvm/test/CodeGen/Mips/selne.ll index 6fe9e48279877..ff4cd116441c0 100644 --- a/llvm/test/CodeGen/Mips/selne.ll +++ b/llvm/test/CodeGen/Mips/selne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selnek.ll b/llvm/test/CodeGen/Mips/selnek.ll index f38ab246e60f4..f21693aeff0c7 100644 --- a/llvm/test/CodeGen/Mips/selnek.ll +++ b/llvm/test/CodeGen/Mips/selnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selpat.ll b/llvm/test/CodeGen/Mips/selpat.ll index d765acbab33a1..dafe40e763636 100644 --- a/llvm/test/CodeGen/Mips/selpat.ll +++ b/llvm/test/CodeGen/Mips/selpat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll index da57b92e8f6df..912998ab9d038 100644 --- a/llvm/test/CodeGen/Mips/unalignedload.ll +++ b/llvm/test/CodeGen/Mips/unalignedload.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } diff --git a/llvm/test/DebugInfo/Mips/tls.ll b/llvm/test/DebugInfo/Mips/tls.ll index baf346fe035ba..5a00d6b757c36 100644 --- a/llvm/test/DebugInfo/Mips/tls.ll +++ b/llvm/test/DebugInfo/Mips/tls.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -march=mips -mcpu=mips32r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-WORD -; RUN: llc -O0 -march=mips64 -mcpu=mips64r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-DWORD +; RUN: llc -O0 -mtriple=mips-elf -mcpu=mips32r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-WORD +; RUN: llc -O0 -mtriple=mips64-elf -mcpu=mips64r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-DWORD @x = thread_local global i32 5, align 4, !dbg !0