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[RISCV] Add TT-Ascalon-d8 processor #115100

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Merged
merged 4 commits into from
Nov 19, 2024
Merged

[RISCV] Add TT-Ascalon-d8 processor #115100

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246f137
[RISCV] Add TT-Ascalon-d8 processor
ppenzin Nov 5, 2024
6f980c7
Fix ident and features
ppenzin Nov 7, 2024
34cc9f8
Rewrite extension list using RVA23
ppenzin Nov 9, 2024
20305c8
One feature check per line
ppenzin Nov 12, 2024
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55 changes: 55 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,61 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s
// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s
// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" "-target-feature" "+a"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" "-target-feature" "+d"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" "-target-feature" "+v"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" "-target-feature" "+zicbom"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" "-target-feature" "+zcb"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
// MCPU-VEYRON-V1: "-target-feature" "+m"
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2 changes: 2 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Expand Up @@ -41,6 +41,7 @@
// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-d8
// RISCV64-SAME: {{^}}, veyron-v1
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{$}}
Expand Down Expand Up @@ -87,6 +88,7 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -185,6 +185,7 @@ Changes to the RISC-V Backend
* The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally.
* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
* `-mcpu=syntacore-scr7` was added.
* `-mcpu=tt-ascalon-d8` was added.
* The `Zacas` extension is no longer marked as experimental.
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
are no longer marked as experimental.
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47 changes: 47 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
NoSchedModel,
[Feature64Bit,
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@lukel97 lukel97 Nov 7, 2024

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You can include all the RVA23U64 features with a !listconcat, similar to what the other processors have done with RVA22U64

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@ppenzin ppenzin Nov 9, 2024

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Thanks, addressed

FeatureStdExtI,
FeatureStdExtZifencei,
FeatureStdExtZicsr,
FeatureStdExtZicntr,
FeatureStdExtZihpm,
FeatureStdExtZihintpause,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtV,
FeatureStdExtZvl256b,
FeatureStdExtZfh,
FeatureStdExtZvfh,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureStdExtZimop,
FeatureStdExtH,
FeatureStdExtZihintntl,
FeatureStdExtZfa,
FeatureStdExtZkt,
FeatureStdExtZcb,
FeatureStdExtZvbb,
FeatureStdExtZvbc,
FeatureStdExtZawrs,
FeatureStdExtZvkng,
FeatureStdExtZicond,
FeatureStdExtSvnapot,
FeatureStdExtSvpbmt,
FeatureStdExtSvinval,
FeatureStdExtZfbfmin,
FeatureStdExtZvfbfmin,
FeatureStdExtZvfbfwma,
FeatureUnalignedScalarMem,
FeatureUnalignedVectorMem],
[TuneNoDefaultUnroll,
TuneOptimizedZeroStrideLoad,
FeaturePostRAScheduler]>;

def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
NoSchedModel,
[Feature64Bit,
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