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[RISCV] Lower fixed-length mload/mstore for zvfhmin/zvfbfmin #115145

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Merged
merged 1 commit into from
Nov 7, 2024
Merged

[RISCV] Lower fixed-length mload/mstore for zvfhmin/zvfbfmin #115145

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8 changes: 3 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1339,9 +1339,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VECTOR_SHUFFLE, ISD::VECTOR_COMPRESS},
VT, Custom);

// FIXME: mload, mstore, vp_gather/scatter can be
// hoisted to here.
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MGATHER, ISD::MSCATTER},
// FIXME: vp_gather/scatter can be hoisted to here.
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
ISD::MGATHER, ISD::MSCATTER},
VT, Custom);
setOperationAction({ISD::VP_LOAD, ISD::VP_STORE,
ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
Expand Down Expand Up @@ -1409,8 +1409,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR}, VT,
Custom);

setOperationAction({ISD::MLOAD, ISD::MSTORE}, VT, Custom);

setOperationAction({ISD::VP_GATHER, ISD::VP_SCATTER}, VT, Custom);

setOperationAction({ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV,
Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -239,8 +239,12 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
return false;

return TLI->isLegalElementTypeForRVV(ElemType);

// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
return TLI->isLegalElementTypeForRVV(ElemType) ||
(DataTypeVT.getVectorElementType() == MVT::bf16 &&
ST->hasVInstructionsBF16Minimal()) ||
(DataTypeVT.getVectorElementType() == MVT::f16 &&
ST->hasVInstructionsF16Minimal());
}

bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
Expand Down
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