diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 0704b57ff9565..ba4442fe613c7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -534,9 +534,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .legalIf(typeIsScalarFPArith(0, ST))
       .lowerFor({s32, s64});
 
-  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
-      .legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
-      .widenScalarToNextPow2(0)
+  auto &FPToIActions = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI});
+  FPToIActions.legalIf(all(typeInSet(0, {sXLen}), typeIsScalarFPArith(1, ST)));
+  if (ST.is64Bit())
+    FPToIActions.customIf(all(typeInSet(0, {s32}), typeIsScalarFPArith(1, ST)));
+  FPToIActions.widenScalarToNextPow2(0)
       .minScalar(0, s32)
       .libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
       .libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});
@@ -1171,6 +1173,10 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
     return RISCV::G_CLZW;
   case TargetOpcode::G_CTTZ:
     return RISCV::G_CTZW;
+  case TargetOpcode::G_FPTOSI:
+    return RISCV::G_FCVT_W_RV64;
+  case TargetOpcode::G_FPTOUI:
+    return RISCV::G_FCVT_WU_RV64;
   }
 }
 
@@ -1229,6 +1235,15 @@ bool RISCVLegalizerInfo::legalizeCustom(
     Helper.Observer.changedInstr(MI);
     return true;
   }
+  case TargetOpcode::G_FPTOSI:
+  case TargetOpcode::G_FPTOUI: {
+    Helper.Observer.changingInstr(MI);
+    Helper.widenScalarDst(MI, sXLen);
+    MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
+    MI.addOperand(MachineOperand::CreateImm(RISCVFPRndMode::RTZ));
+    Helper.Observer.changedInstr(MI);
+    return true;
+  }
   case TargetOpcode::G_IS_FPCLASS: {
     Register GISFPCLASS = MI.getOperand(0).getReg();
     Register Src = MI.getOperand(1).getReg();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index aa06cb4d5327c..829c0ac92c52a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -149,6 +149,8 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
                                        const MachineRegisterInfo &MRI,
                                        const TargetRegisterInfo &TRI) const {
   switch (MI.getOpcode()) {
+  case RISCV::G_FCVT_W_RV64:
+  case RISCV::G_FCVT_WU_RV64:
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FCMP:
@@ -432,6 +434,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
     break;
   }
+  case RISCV::G_FCVT_W_RV64:
+  case RISCV::G_FCVT_WU_RV64:
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
   case RISCV::G_FCLASS: {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index 424623360d255..32e63977b51e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -49,6 +49,22 @@ def G_CTZW : RISCVGenericInstruction {
 }
 def : GINodeEquiv<G_CTZW, riscv_ctzw>;
 
+// Pseudo equivalent to a RISCVISD::FCVT_W_RV64.
+def G_FCVT_W_RV64 : RISCVGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src, untyped_imm_0:$frm);
+  let hasSideEffects = false;
+}
+def : GINodeEquiv<G_FCVT_W_RV64, riscv_fcvt_w_rv64>;
+
+// Pseudo equivalent to a RISCVISD::FCVT_WU_RV64.
+def G_FCVT_WU_RV64 : RISCVGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src, untyped_imm_0:$frm);
+  let hasSideEffects = false;
+}
+def : GINodeEquiv<G_FCVT_WU_RV64, riscv_fcvt_wu_rv64>;
+
 // Pseudo equivalent to a RISCVISD::FCLASS.
 def G_FCLASS : RISCVGenericInstruction {
   let OutOperandList = (outs type0:$dst);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 21583825405d5..b5e1298c7770a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -534,7 +534,7 @@ def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$i
           (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
 } // Predicates = [HasStdExtZdinx, IsRV32]
 
-let Predicates = [HasStdExtD] in {
+let Predicates = [HasStdExtD, IsRV32] in {
 
 // double->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, FRM_RTZ)>;
@@ -553,7 +553,7 @@ def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, FRM_RMM)>;
 // [u]int->double.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1, FRM_RNE)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1, FRM_RNE)>;
-} // Predicates = [HasStdExtD]
+} // Predicates = [HasStdExtD, IsRV32]
 
 let Predicates = [HasStdExtZdinx, IsRV32] in {
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index da3f207a2faf7..0f2b0bb8a78c6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -720,7 +720,7 @@ def : Pat<(f32 (bitconvert (i32 GPR:$rs1))), (EXTRACT_SUBREG GPR:$rs1, sub_32)>;
 def : Pat<(i32 (bitconvert FPR32INX:$rs1)), (INSERT_SUBREG (XLenVT (IMPLICIT_DEF)), FPR32INX:$rs1, sub_32)>;
 } // Predicates = [HasStdExtZfinx]
 
-let Predicates = [HasStdExtF] in {
+let Predicates = [HasStdExtF, IsRV32] in {
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, FRM_RTZ)>;
 def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, FRM_RTZ)>;
@@ -738,9 +738,9 @@ def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, FRM_RMM)>;
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, FRM_DYN)>;
-} // Predicates = [HasStdExtF]
+} // Predicates = [HasStdExtF, IsRV32]
 
-let Predicates = [HasStdExtZfinx] in {
+let Predicates = [HasStdExtZfinx, IsRV32] in {
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, FRM_RTZ)>;
 def : Pat<(i32 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_WU_S_INX $rs1, FRM_RTZ)>;
@@ -758,7 +758,7 @@ def : Pat<(i32 (any_lround FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, FRM_RMM)>;
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_INX $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_INX $rs1, FRM_DYN)>;
-} // Predicates = [HasStdExtZfinx]
+} // Predicates = [HasStdExtZfinx, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
 // Moves (no conversion)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 0d3127e0d5abe..ccf13e07ef193 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -480,7 +480,7 @@ def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (INSERT_SUBREG (XLenVT (IMPLICIT_
 def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>;
 } // Predicates = [HasStdExtZhinxmin]
 
-let Predicates = [HasStdExtZfh] in {
+let Predicates = [HasStdExtZfh, IsRV32] in {
 // half->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, 0b001)>;
 def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_H $rs1, 0b001)>;
@@ -500,7 +500,7 @@ def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_W $rs1, FRM_DYN)>;
 def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_WU $rs1, FRM_DYN)>;
 } // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZhinx] in {
+let Predicates = [HasStdExtZhinx, IsRV32] in {
 // half->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, 0b001)>;
 def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_H_INX $rs1, 0b001)>;
@@ -518,7 +518,7 @@ def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_RMM)>;
 // [u]int->half. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_INX $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_INX $rs1, FRM_DYN)>;
-} // Predicates = [HasStdExtZhinx]
+} // Predicates = [HasStdExtZhinx, IsRV32]
 
 let Predicates = [HasStdExtZfh, IsRV64] in {
 // Use target specific isd nodes to help us remember the result is sign
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
index 11a3f47ea7f14..eb5558b872698 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
@@ -19,9 +19,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s16) = COPY $f10_h
-    %1:gprb(s32) = G_FPTOSI %0(s16)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_W_RV64 %0(s16), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -42,9 +41,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s16) = COPY $f10_h
-    %1:gprb(s32) = G_FPTOUI %0(s16)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_WU_RV64 %0(s16), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
index afa53c8de76db..9c3b306cd3394 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
@@ -19,9 +19,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s32) = COPY $f10_f
-    %1:gprb(s32) = G_FPTOSI %0(s32)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_W_RV64 %0(s32), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -42,9 +41,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s32) = COPY $f10_f
-    %1:gprb(s32) = G_FPTOUI %0(s32)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_WU_RV64 %0(s32), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -109,9 +107,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s64) = COPY $f10_d
-    %1:gprb(s32) = G_FPTOSI %0(s64)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_W_RV64 %0(s64), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -132,9 +129,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:fprb(s64) = COPY $f10_d
-    %1:gprb(s32) = G_FPTOUI %0(s64)
-    %2:gprb(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:gprb(s64) = G_FCVT_WU_RV64 %0(s64), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
index 12a0d0e4c763c..55bf47dfde32a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
@@ -12,9 +12,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s1) = G_FPTOSI %0(s16)
@@ -33,9 +32,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s1) = G_FPTOUI %0(s16)
@@ -54,9 +52,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s8) = G_FPTOSI %0(s16)
@@ -75,9 +72,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s8) = G_FPTOUI %0(s16)
@@ -96,9 +92,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s16) = G_FPTOSI %0(s16)
@@ -117,9 +112,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s16) = G_FPTOUI %0(s16)
@@ -138,9 +132,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s32) = G_FPTOSI %0(s16)
@@ -159,9 +152,8 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
     %1:_(s32) = G_FPTOUI %0(s16)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
index f233e6279a13d..657d3a43d1239 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
@@ -12,9 +12,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s1) = G_FPTOSI %0(s32)
@@ -33,9 +32,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s1) = G_FPTOUI %0(s32)
@@ -54,9 +52,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s8) = G_FPTOSI %0(s32)
@@ -75,9 +72,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s8) = G_FPTOUI %0(s32)
@@ -96,9 +92,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s16) = G_FPTOSI %0(s32)
@@ -117,9 +112,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s16) = G_FPTOUI %0(s32)
@@ -138,9 +132,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s32) = G_FPTOSI %0(s32)
@@ -159,9 +152,8 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
     %1:_(s32) = G_FPTOUI %0(s32)
@@ -218,9 +210,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s1) = G_FPTOSI %0(s64)
@@ -239,9 +230,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s1) = G_FPTOUI %0(s64)
@@ -260,9 +250,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s8) = G_FPTOSI %0(s64)
@@ -281,9 +270,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s8) = G_FPTOUI %0(s64)
@@ -302,9 +290,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s16) = G_FPTOSI %0(s64)
@@ -323,9 +310,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s16) = G_FPTOUI %0(s64)
@@ -344,9 +330,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s32) = G_FPTOSI %0(s64)
@@ -365,9 +350,8 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
     %1:_(s32) = G_FPTOUI %0(s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
index 37aefa3ecbf0c..d63803f8f5bdf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
@@ -15,14 +15,12 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
-    %1:_(s32) = G_FPTOSI %0(s16)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_W_RV64 %0(s16), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -38,14 +36,12 @@ body:             |
     ; CHECK: liveins: $f10_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s16)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s16) = COPY $f10_h
-    %1:_(s32) = G_FPTOUI %0(s16)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_WU_RV64 %0(s16), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
index adfa458939d12..d5c2875d316cb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
@@ -15,14 +15,12 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
-    %1:_(s32) = G_FPTOSI %0(s32)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_W_RV64 %0(s32), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -38,14 +36,12 @@ body:             |
     ; CHECK: liveins: $f10_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $f10_f
-    %1:_(s32) = G_FPTOUI %0(s32)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_WU_RV64 %0(s32), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -103,14 +99,12 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
-    %1:_(s32) = G_FPTOSI %0(s64)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_W_RV64 %0(s64), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...
@@ -126,14 +120,12 @@ body:             |
     ; CHECK: liveins: $f10_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
-    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $f10_d
-    %1:_(s32) = G_FPTOUI %0(s64)
-    %2:_(s64) = G_ANYEXT %1(s32)
-    $x10 = COPY %2(s64)
+    %1:_(s64) = G_FCVT_W_RV64 %0(s64), 1
+    $x10 = COPY %1(s64)
     PseudoRET implicit $x10
 
 ...