diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 203e14f6cde3e..fe7d4b9d7ccbf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6224,8 +6224,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
       return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
     }
     if (OpOpcode == ISD::UNDEF)
-      // sext(undef) = 0, because the top bits will all be the same.
-      return getConstant(0, DL, VT);
+      // sext(undef) = undef in a conservative way, because not all of the bits
+      // are zero and there is no mechanism tracking the undef part.
+      return getUNDEF(VT);
     break;
   case ISD::ZERO_EXTEND:
     assert(VT.isInteger() && N1.getValueType().isInteger() &&
@@ -6244,8 +6245,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
       return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
     }
     if (OpOpcode == ISD::UNDEF)
-      // zext(undef) = 0, because the top bits will be zero.
-      return getConstant(0, DL, VT);
+      // zext(undef) = undef in a conservative way, because not all of the bits
+      // are zero and there is no mechanism tracking the undef part.
+      return getUNDEF(VT);
 
     // Skip unnecessary zext_inreg pattern:
     // (zext (trunc x)) -> x iff the upper bits are known zero.
diff --git a/llvm/test/CodeGen/X86/zext-sext.ll b/llvm/test/CodeGen/X86/zext-sext.ll
index 25929ecbde76f..766512afc2a7e 100644
--- a/llvm/test/CodeGen/X86/zext-sext.ll
+++ b/llvm/test/CodeGen/X86/zext-sext.ll
@@ -77,5 +77,15 @@ entry:
   %alphaXbetaY = add i64 %alphaX, %tmp115
   %transformed = add i64 %alphaXbetaY, 9040145182981852475
   store i64 %transformed, ptr %d, align 8
+  %tmp200 = zext i16 undef to i32
+  %tmp201 = zext i16 undef to i32
+  %tmp202 = shl i32 %tmp201, 16
+  %tmp203 = or i32 %tmp200, %tmp202
+  store i32 %tmp203, ptr %a, align 4
+  %tmp210 = sext i16 undef to i32
+  %tmp211 = sext i16 undef to i32
+  %tmp212 = shl i32 %tmp211, 16
+  %tmp213 = or i32 %tmp210, %tmp212
+  store i32 %tmp213, ptr %b, align 4
   ret void
 }